Texas Instruments Corporation

Bob D Strong

Anand Seshadri

Jeffrey A Niehaus

Sudhir Kumar Madan

Kevin M Ovens

Joe W McPherson

Homi C Mogul

Robert G Fleck

Stephen Li

A static random access memory array (200) with power supplies and an array biasing scheme is disclosed. A power supply (202) has an output voltage that is applied to the bitlines (40). The output voltage pre-charges the bitlines (40) to read from the memory cells (10). An array power supply (204) has an array voltage that is applied to the memory cells. The array voltage is higher than the output voltage. The array power supply (204) is drived by boosting the output voltage of the power supply (202).

Apparatus and method for static random access memory array

A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).

Depletion mode MOS capacitor with patterned V.sub.T implants

A semiconductor device includes a first transistor (52) and gated diode (50) formed at a face of a semiconductor layer (56). The first transistor (52) includes a source region (60a), a drain region (60b), a gate oxide layer (62), and a conductive gate (64). The gated diode (54) includes a first moat region (66a), a second moat region (66b), a gate oxide layer (68), and a conductive gate (70). A first conductor (77) connects the conductive gate (70) of the gated diode (54) to the semiconductor layer (56) and a second conductor (76) connects the moat regions (66a, 66b) of the gated diode (54) to the conductive gate (64) of the first transistor (52). Gated diode (54) has a reduced breakdown voltage relative to the gate oxide layer (62) of first transistor (52) and thus establishes a leakage path to semiconductor layer (56) to direct leakage current to semiconductor layer (56), thereby inhibiting charge from accumulating on the gate oxide layer (62) of first transistor (52).

Method and apparatus for protecting gate oxide from process-induced

Depletion mode MOS capacitor with patterned V.sub.t implants

A TTL gate (22) includes a current generating circuit (24) comprising an NPN transistor (30) having its base coupled to a diode (24) and its emitter coupled to one of the gate's output transistors (14). Transistor (30) enables diode (24) to deliver a high current of short duration to the output OUT responsive to a low-to-high output transition. The current provides low-to-high output transition while protecting output transistor (14) from damaging currents caused by a short circuit at output OUT.

Circuit for limiting the short circuit output current

A digital crossbar switch for switching data from an input/output data bus to an internal data bus and to the same or another input/output data bus which includes a plurality of multiplexer logic units, an m-bit internal data bus coupled to each of said multiplexer logic units where m is an integer, and a plurality of n-bit input/output data buses one connected to each of the multiplexer logic units were n is an integer. The switch further includes an m/n to 1 multiplexer, where m/n is an integer, in each multiplexer logic unit. The m/n to 1 multiplexer has an input control to the internal data bus and an output coupled to a corresponding one of the input/output data buses and is operative in response to a configuration control signal to switch a selected n-bits of data from the internal data bus to the corresponding input/output data bus. A memory storage for storing configuration control signals is coupled to the m/n to 1 multiplexer.

Digital crossbar switch

A high speed interstage STL buffer (27) is disclosed having a low threshold and high driving capability. A first Schottky-clamped grounded emitter transistor (28) receives input signals through a Schottky steering diode (38) and inverts the input signal. The input signal is applied in parallel through a Schottky steering diode (20) to a second Schottky-clamped grounded emitter transistor (12). The collector (22) of the second transistor (12) provides an output of the buffer (27) for driving load current in one direction with respect to the buffer output. A third transistor (40) connected as an emitter follower has the emitter (42) thereof connected to the buffer output for driving load currents in the other direction. The base (46) of the emitter follower transistor (40) is coupled by a Schottky steering diode (50) to the collector (32) of the first transistor (28). The steering diodes (20, 38, 50) have a forward threshold voltage less than that of the Schottky-barrier diodes used to clamp the base-collector junctions of the first and second transistors (28, 12).

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Sachse, TX, United States of America

Bob D Strong