Samsung Electronics Co., Ltd.

Bob Brennan

Hongzhong Zheng

Krishna Teja Malladi

Dimin Niu

Shuangchen Li

Fred Worley

Harry Rogers

Gunneswara Rao Marripudi

Chaohong Hu

Tameesh Suri

Arash Rezaei

A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.

Scaling out architecture for dram-based processing unit (DPU)

Scaling out architecture for DRAM-based processing unit (DPU)

A system includes a dynamic random-access memory (DRAM); and a storage device comprising a power source and a persistent store. The storage device is configured to provide reserve power to the DRAM. Data stored in the DRAM is transferred to a reserved storage in the persistent store of the storage device in a power loss event using the reserve power.

Storage device with a power source and persistent store that provides backup power to DRAM in a power loss event

An embodiment includes a storage device, comprising: a memory; and a controller including a memory interface coupled to the memory, the controller configured to: receive write data to write to an address associated with first data stored in the memory and a first differentially compressed value stored in the memory; calculate a second differentially compressed value based on the write data and the first data; store the second differentially compressed value in the memory; and change the association of the address to reference the second differentially compressed value instead of the first differentially compressed value.

Versioning storage devices and methods

A deduplication memory module, which is configured to internally perform memory deduplication, includes a hash table memory for storing multiple blocks of data in a hash table array including hash tables, each of the hash tables including physical buckets and a plurality of virtual buckets each including some of the physical buckets, each of the physical buckets including ways, an address lookup table memory (ALUTM) including a plurality of pointers indicating a location of each of the stored blocks of data in a corresponding one of the physical buckets, and a buffer memory for storing unique blocks of data not stored in the hash table memory when the hash table array is full, a processor, and memory, wherein the memory has stored thereon instructions that, when executed by the processor, cause the memory module to exchange data with an external system.

Dedupe DRAM system algorithm architecture

Growing community of inventors

Santa Clara, CA, United States of America

Bob Brennan