Freescale Semiconductor,inc.

Broadcom Corporation

Mysticom Ltd.

Mellanox Technologies, Ltd.

Boaz Shahar

Eyran Lida

Oren Issac Wolach

Yuval Itkin

David Avishai

Haim Kupershmidt

Stefania Gandal

Noam Sheffer

Aviram Hertzberg

Nir Eilam

Freddy Gabbay

Eyal Soha

Dan Beygelman

Liat Kochavi

Michal Shmueli

Eyal Massad

David Sitbon

Uriya Stern

Yigal Edery

In one embodiment, a device includes a memory to store a first public key indicating security ownership of the device by a first owner, an interface to receive a signature of an intermediate public key signed by a first owner signing service with a first private key, and processing circuitry to load the intermediate public key in the memory, responsively to authenticating the signature, and remove the first public key from the memory, and wherein the interface is to receive a second public key and a signature of the second public key signed by a second owner signing service with an intermediate private key, the processing circuitry is to load a second public key in the memory indicating ownership has been transferred to the second owner responsively to authenticating the signature of the second public key with the intermediate public key, and remove the intermediate public key from the memory.

Device control transfer

Methods, systems, and computer program products are provided for inserting the packet into a tail of a linked list buffer, and the linked list buffer includes a plurality of Buffer Descriptors (BD), a HEAD pointer pointing to a null Buffer Descriptor (NullBD) and a NULLBD pointer. The NULLBD pointer is switched to point to the NullBD and the HEAD pointer to point to a valid BD which represents a memory address of payload data in the packet to be transmitted. Upon transmission of the packet, the HEAD pointer is converted to point to the NullBD and the NULLBD pointer to point to the valid BD. The valid BD pointed by the NULLBD pointer is finally transferred to a free linked list buffer so that the NULLBD pointer points to no memory address.

Non-semaphore linked list management

A method for transmitting packets, the method includes receiving multiple packets at multiple queues. The method is characterized by dynamically defining fixed priority queues and weighted fair queuing queues, and scheduling a transmission of packets in response to a status of the multiple queues and in response to the definition. A device for transmitting packets, the device includes multiple queues adapted to receive multiple packets. The device includes a circuit that is adapted to dynamically define fixed priority queues and weighted fair queuing queues out of the multiple queues and to schedule a transmission of packets in response to a status of the multiple queues and in response to the definition.

Hybrid method and device for transmitting packets

An apparatus for enabling booting from a NAND flash memory comprises a NAND flash controller connected to the NAND flash memory, wherein the NAND flash memory is configured to include at least a starter section for storing boot code, the starter section includes a predefined number of blocks to store copies of the boot code duplicated in a configurable number of blocks; and a fetch emulator for fetching a valid and complete starter block that includes the boot code.

Apparatus and method thereof for reliable booting from NAND flash memory

A device and method for processing information fragments, the method includes: receiving multiple information fragments from multiple communication paths; wherein the each information fragment is associated with a cyclic serial number indicating of a generation time of the information fragment; storing the multiple information fragments in multiple input queues, each input queue being associated with a communication path out of the multiple communication paths; determining whether at least one serial number associated with at least one valid information fragment positioned in a head of one of the multiple input queues is located within a pre-rollout serial number range; mapping, in response to the determination, serial numbers associated with each of the valid information fragment positioned in the heads of the multiple input queues to at least one serial number range that differs from the pre-rollout serial number range; and sending to an output queue information fragment metadata associated with a minimal valued serial number out of the serial numbers associated with each of the valid information fragment positioned in the heads of the multiple input queues.

Method for processing information fragments and a device having information fragment processing capabilities

A method for recoding an input sequence of words, including assigning a respective bit-grade to at least one of the bits in a first word in the input sequence, deriving candidate words from the first word in response to the respective bit-grade, and inserting one of the candidate words into each of a plurality of candidate sequences, so that each of the candidate sequences contains one of the candidate words. The method further includes adding subsequent words to the candidate sequences, the subsequent words consisting of a further candidate word derived from a further word in the input sequence, computing respective sequence parameters for the candidate sequences, based on a relation between the candidate words and the subsequent words in the candidate sequences, selecting one of the candidate sequences in response to the sequence parameters, and outputting one of the candidate words contained in the selected candidate sequence.

Error correction of balanced codeword sequence

A receiver for deserializing a stream of data bits, including a single clock which is adapted to generate a first plurality of clock phases, and a sample generator which is adapted to sample the stream so as to generate initial data values of each of the bits at times defined by the first plurality of clock phases. The receiver further includes digital circuitry which is adapted to group the initial values into a second plurality of sampling phase sets, according to the clock phases at which the values were sampled, and assign each of the phase sets a respective grade in response to at least some of the initial values. The circuitry selects a decoding phase set from the phase sets in response to the respective grades, and decodes the stream in response to initial values of the decoding phase set to generate decoded values of the consecutive bits.

Deserializer

Packets of data from multiple queues are transferred onto a single channel. Each queue has associated with it a data rate for servicing a packet within the queue. Each queue has an integer that, relative to the other numbers, represents is inversely related to the assigned data rate. Each queue has associated with it a counter and that is loaded with its corresponding integer. The counter values are compared, and the queue corresponding to the lowest counter value has a packet coupled to the channel. The counter of the selected queue is incremented by its integer. The next queue that is selected is the one that corresponds to the counter with the lowest count value after the counter that corresponds to the previously selected queue has been updated.

Growing community of inventors

Raanana, Israel

Boaz Shahar