Applied Materials, Inc.

Arm Limited

Facebook Technologies, LLC

Bo Zheng

Avgerinos V Gelatos

Xinyu Fu

Lalit Gupta

Srinivas Gandikota

Yu Lei

Sang Ho Yu

Fakhruddin Ali Bohra

Bhushan N Zope

Mei Yin Chang

Ling Chen

Arvind Sundarrajan

Seshadri Ganguli

Gus Wai-Yan Yeung

Salvador P Umotoy

El Mehdi Boujamaa

Mathew Abraham

Andy Wangkun Chen

Nicolaas Klarinus Johannes Van Winkelhoff

Michael Sterling Jackson

Hougong Wang

Hua Ai

Yew Keong Chong

Girish Anant Dixit

Xiaoxiong Yuan

Raymond Hoiman Hung

Vivek Nautiyal

Sang-Ho Yu

Jitendra Dasani

Mohan K Bhan

Hyman W H Lam

Anshul Vyas

Nimish Sharma

George McNeil Lattimore

Fusen E Chen

Alfred W Mak

Xin Sheng Guo

Akshay Kumar

Benjamin Schmiege

Frank Guo

Vivek Asthana

Keith K Koai

Samuel C Wilson

Zhonghui Alex Wang

Hetansh Pareshbhai Shah

Hou Gong Wang

Dmitry Lubomirsky

Rajeev Bajaj

John C Forster

Karl Anthony Littau

Jeffrey W Anthis

Harald Herchen

Yixiong Yang

Chien-Teh Kao

Kai Wu

Christophe Marcadal

Anzhong Chang

Murali K Narasimhan

Ken Kaung Lai

Shri Sagar Dwivedi

Cyrille Nicolas Dray

Siqing Lu

Lily L Pang

Jungtae Kwon

John Vincent Schmitt

Martin Jay Kinkade

Son Trinh

Martin Jeff Salinas

Guoqiang Jian

Joshua Warren Bingham

Brian Reed

Satinderjit Singh

Ping Jian

Xiaoxiong (John) Yuan

Rajkumar Jakkaraju

Hyman Lam

Joshua Davies

Linh Thanh

Timothy E Levine

Bevan Vo

Justin Jones

Shrisagar Dwivedi

Manish Hamkar

Umesh M Kellkar

Renren He

Katherine Suzi Torigoe

Stephen Voss

Ulrik Skov

Ashish Bhardwaj

Durgesh Kumar Dubey

Michael Jackson

Ai Hua

San Ho Yu

Various implementations described herein refer to a method for providing memory with one or more banks. The method may include coupling read-write column multiplexer circuitry to the memory via bitlines including coupling a write column multiplexer to the bitlines for write operations and coupling a read column multiplexer to the bitlines for read operations. The method may include performing concurrent read operations and write operations in the one or more banks of the memory with the write column multiplexer and the read column multiplexer via the bitlines.

Concurrent memory access operations

Various implementations described herein refer to a method for providing single port memory with multiple different banks having a first bank and a second bank that is different than the first bank. The method may include coupling multiple wordlines to the single port memory including coupling a first wordline to the first bank and coupling a second wordline to the second bank. The method may include performing multiple memory access operations concurrently in the single port memory.

Concurrent access techniques utilizing wordlines with the same row address in single port memory

In a particular implementation, a circuit comprises: a memory array including a plurality of bit cells, where each of the bit cells are coupled to a respective bit path; a first multiplexer comprising a plurality of column address locations, where each of the plurality of column address locations is coupled to the memory array and corresponds to a respective bit path capacitance; and a variable capacitance circuit coupled to a reference path and configured to substantially match reference path capacitance to each of the respective bit path capacitances.

Circuits and methods for capacitor modulation

Various implementations described herein refer to a method for providing single port memory with a bitcell array arranged in columns and rows. The method may include coupling a wordline to the single port memory including coupling the wordline to the columns of the bitcell array. The method may include performing multiple memory access operations concurrently in the single port memory including performing a read operation in one column of the bitcell array using the wordline while performing a write operation in another column of the bitcell array using the wordline, or performing a write operation in one column of the bitcell array using the wordline while performing a read operation in another column of the bitcell array using the same wordline.

System device and method for providing single port memory access in bitcell array by tracking dummy wordline

Various implementations described herein are directed to an implementation of a higher order multiplexer using lower order multiplexers. In an embodiment, the implementation requires a slight modification to the existing circuitry design of the lower multiplexers. A plurality of multiplexers may be coupled with each other such that a common input port and output port is formed. Using an enable signal, only one of the coupled multiplexers may be enabled at a time while the remaining multiplexers are switched off. Therefore, upon receiving a select signal indicating an address of a memory cell, the lower multiplexers coupled together function as a higher order multiplexer in selecting the appropriate column corresponding to the memory cell.

Circuit architecture to derive higher mux from lower mux design

Various implementations described herein are directed to a device having memory circuitry with a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.

Write assist circuitry

A display device may include (i) a display panel, (ii) a housing surrounding at least a portion of the display panel, (iii) an audio trench peripherally surrounding at least a portion of the display panel, the audio trench including a trench opening in a front side of the housing between a frame region and a peripheral region, and (iv) at least one speaker driver disposed between the display panel and a back side of the housing, the at least one speaker driver including a sound radiating surface positioned to direct sound waves into an acoustic chamber defined between the at least one speaker driver and the display panel, wherein a chamber opening is located between a lateral periphery of the acoustic chamber and the audio trench. Various other systems, devices, assemblies, and methods are also disclosed.

Display device with peripherally surrounding audio trench and acoustic port

Methods for depositing a metal layer in a feature definition of a semiconductor device are provided. In one implementation, a method for depositing a metal layer for forming a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a metal layer on a substrate and annealing the metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the metal layer on the substrate, exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process until a predetermined thickness of the metal layer is achieved.

Method of enabling seamless cobalt gap-fill

The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.

Pre-clean of silicon germanium for pre-metal contact at source and drain and pre-high K at channel

Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

Power-on-reset circuit

Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a contact metal layer on a substrate and annealing the contact metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the contact metal layer on the substrate, exposing the portion of the contact metal layer to a plasma treatment process, and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the contact metal layer to a plasma treatment process until a predetermined thickness of the contact metal layer is achieved.

Various implementations described herein are directed to an integrated circuit with memory circuitry having an array of bitcells that are accessible via multiple bitlines. The integrated circuit may include a write driver coupled to at least one bitline of the multiple bitlines through a column multiplexer. The integrated circuit may include a pass transistor coupled to the write driver and the column multiplexer via a write data line. The integrated circuit may include a charge storage device coupled between the pass transistor and write assist enable circuitry. The integrated circuit may include a transmission gate coupled to a gate of the write driver. The integrated circuit may include a clamp transistor coupled between the gate of write driver and the charge storage device such that the clamp transistor receives a voltage assist signal from the charge storage device at the gate of the write driver.

Bitline write assist circuitry

Methods for selectively depositing a metal silicide layer are provided herein. In some embodiments, a method of selectively depositing a metal silicide layer includes: (a) providing a substrate having a first layer to a process chamber, wherein the first layer comprises a first surface and a feature formed in the first surface comprising an opening defined by one or more sidewalls and a bottom surface wherein the sidewalls comprise one of silicon oxide or silicon nitride and wherein the bottom surface comprises at least one of silicon or germanium; (b) exposing the substrate to a precursor gas comprising a metal halide; (c) purging the precursor gas from the process chamber using an inert gas; (d) exposing the substrate to a silicon containing gas; (e) purging the silicon containing gas from the process chamber using an inert gas; (f) repeating (b)-(e) to selectively deposit a metal silicide along the bottom surface to a predetermined thickness; and (g) annealing the substrate after depositing the metal silicide layer.

Methods for selective deposition of metal silicides via atomic layer deposition cycles

Pre-clean of silicon germanium for pre-metal contact at source and drain and pre-high k at channel

Growing community of inventors

Saratoga, CA, United States of America

Bo Zheng