Apple Inc.

Bo Zhao

Michael A Dreesen

Jaroslav Raszka

Amrinder S Barn

Pangjie Xu

Joao Pedro Da Silva Cerqueira

Steven Lu

A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal.

Multi-chain measurement circuit

A delay circuit with multiple dependencies on various environmental parameters is disclosed. The delay circuit is configured to receive an input signal. The delay circuit includes a first circuit configured to generate a first amount of delay, wherein the first amount of delay has a direct relationship to a first environmental parameter. The delay circuit also includes a second circuit configured to generate a second amount of delay such that the second amount of delay has an inverse relationship to a second environmental parameter. The delay circuit is configured to generate a delayed output signal based on the first and second amounts of delay generated by the first and second circuits.

Delay circuit with multiple dependencies

In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.

Sense amplifier flip-flop with embedded scan logic and level shifting functionality

A level shifter that supports wide voltage range operation by adaptively boosting local supply voltage to its input stage. The level shifter may interface an input (low) voltage domain and an output (high) voltage domain. In the level shifter, an input stage may receive an input signal from the input voltage domain, and an output stage may generate an output signal to be sent to the output voltage domain. In the level shifter, the power supply to the low-voltage input stage is automatically and adaptively boosted to effectuate level conversion of the input signal. A boost control signal is generated when the output signal fails to switch or is slow to switch in response to a corresponding switching of the input signal. In this manner, the voltage operating range of the level shifter is increased. Because boosting is engaged only when needed, the level shifter provides efficient operation with self-adaptability.

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Cupertino, CA, United States of America

Bo Zhao