Micron Technology Incorporated

Bo Zhao

Lifang Xu

Adam L Olson

Nancy M Lomeli

Matthew J King

Matthew Park

Jason Reece

Michael J Gossman

Justin B Dorhout

David A Kewley

Xiaosong Zhang

M Jared Barclay

Shruthi Kumara Vadivel

Biow Hiem Ong

Martin Jared Barclay

Joel D Peterson

Tien Minh Quan Tran

Eldon Nelson

Kah Sing Chooi

Zhen Feng Yow

A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.

Microelectronic devices including stadium structures

A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.

Microelectronic devices and related methods of forming microelectronic devices

Methods of forming microelectronic devices, and related microelectronic devices, and electronic systems

A method used in forming integrated circuitry comprises forming a stack of vertically-alternating tiers of different composition materials. A stair-step structure is formed into the stack and an upper landing is formed adjacent and above the stair-step structure. The stair-step structure is formed to comprise vertically-alternating tiers of the different composition materials. A plurality of stairs individually comprise two of the tiers of different composition materials. At least some of the stairs individually have only two tiers that are each only of a different one of the different composition materials. An upper of the stairs that is below the upper landing comprises at least four of the tiers of different composition materials. Structure independent of method is disclosed.

Integrated circuitry, memory integrated circuitry, and methods used in forming integrated circuitry

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Boise, ID, United States of America

Bo Zhao