University of Electronic Science and Technology of China

Institute of Electronic and Information Engineering of Uestc in Guangdong

Sichuan University

Institute of Electronic and Information Engineering in Dongguan, Uestc

Electronic and Information Engineering in Dongguan, Uestc

Bo Zhang

Ming Qiao

Zhuo Wang

Zehong Li

Jinping Zhang

Yong Fan

Min Ren

Zekun Zhou

Xin Ming

Zhengkang Wang

Xiaorong Luo

Yue Shi

Ruidi Wang

Zhaoji Li

Yujian Cheng

Xiaobo Yang

Ping Luo

Kaijun Song

Zhao Qi

Wentong Zhang

Bingli Dai

Xianqi Lin

Zhongqian Niu

Jicong Zhang

Xuan Zhang

Jianwen Cao

Shaowei Zhen

Yi Hu

Ke Liu

Yafei Wu

Jinfan Zhang

Zhi Chen

Wei Gao

Yunkun Wang

Yandong Yuan

Jiahao Zhang

Di Gao

Fu Peng

Linrong He

Rongrong Zhu

Chunlan Lai

Chunxu Bai

Chao Yang

Jie Wei

Dong Fang

Nailong He

Yuanyuan Tu

Yibing Wang

Wenliang Liu

Yonghong Zhang

Longfei Liang

Yajuan He

Jingxiu Liu

Yuci Lin

Yi Bu Li

Jie Liu

Ke Zhang

Jun Xu

Tao Li

Chao Liu

Hongbin Wang

Xiang Li

Junfeng Wu

Tao Sun

Xi Hu

Qing Liu

Linhua Huang

Yang Yu

Zhihe Zhao

Qi Zhou

Li Hu

Xin Yao

Lei Luo

Chi Xie

Junyuan Rong

Zhiheng Su

Zuao Wang

Shilei Li

Li Ye

Ze-kun Zhou

Jiamu Xiao

Jun-Lin Qian

Danye Liang

Xiao-Lin Liu

Wenlin Zhang

Yumeng Zhang

Qifei Xu

Cong Di

Shuai Mao

Jingzhi Xiong

Gaoqiang Deng

Fan Zhao

Xudong Feng

Kun Zhou

Yanran Ding

He Tang

Siyu Deng

Dongfa Ouyang

Hongming Yu

Wanjun Chen

A new variable selective etching technology for thick SOI devices. An SOI material is etched by the following steps: (1) providing an SOI wafer; (2) depositing a composite hard mask with a variable selection ratio to replace a traditional hard mask with an invariable selection ratio; (3) applying a photoresist; (4) mask making, namely defining a to-be-etched region by using a photoetching plate; (5) etching the photoresist in the defined region; (6) etching the composite hard mask; (7) removing the photoresist; (8) etching top silicon by using a second etching method at a first selection ratio; and (9) etching a buried oxide layer by using a third etching method at a second selection ratio. The new variable selective etching technology avoids the damage to a side wall of a deep trench when the buried oxide layer is etched, and does not need to use an excessive thick hard mask.

Variable selective etching technology for thick SOI devices

A termination structure of a super-junction power device has a novel polysilicon resistive field plate at the top of a termination region between a transition region and an edge of the device. By utilizing the regular distribution of potential in the field plate, an additional electric field is introduced at the top of the termination structure to limit the expansion of a non-depletion region and optimize the distribution of charges. The termination structure includes a first doping type epitaxial layer, a second doping type compensation region, a second doping type body region, a second doping type lateral connection layer, a second doping type body contact region, a first doping type source contact region, a gate oxide layer, a passivation layer, a field oxide layer, a gate electrode, a second doping type edge contact region, a polysilicon resistive field plate, a metal layer and the like.

Termination structure of super-junction power device comprising plurality of runway-shaped rings as the resistive field plate

A method for manufacturing a semiconductor device is provided. A drift region and a compensation region are formed through a deep trench etching and a filling technology. A plurality of modulation doping regions are formed at a top of the drift region by an epitaxy and an ion implantation. A modulation region is introduced, wherein the modulation region flexibly modifies capacitance characteristics and achieve improved dynamic characteristics.

Semiconductor device and manufacturing method

A split gate carrier stored trench bipolar transistor (CSTBT) with current clamping PMOS include a P-type buried layer and a split gate electrode with equal potential to an emitter metal on the basis of the traditional CSTBT, which effectively eliminates the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation effect, and helps to improve the trade-off relationship between the on-state voltage drop and the turn-off loss. Moreover, the introduction of a parasitic PMOS structure can reduce the saturation current and improve short-circuit safe operating area of the device, reduce the Miller capacitance, and improve the switching speed of the device and reduce the switching loss of the device. In addition, the split gate CSTBT integrating the split gate electrode and gate electrode in the same trench can shorten the distance between PMOS and NMOS channels.

Split gate CSTBT with current clamping PMOS and manufacturing method thereof

A three-dimensional carrier stored trench IGBT and a manufacturing method thereof are provided. A P-type buried layer and a split gate electrode with equal potential to an emitter metal is introduced on the basis of the traditional carrier stored trench IGBT, which can effectively eliminate the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation, and at the same time can reduce the on-state voltage drop and improve the trade-off relationship between the on-state voltage drop Vceon and the turn-off loss Eoff. The split gate electrodes is introduced in the Z-axis direction, so that the gate electrodes are distributed at intervals. Therefore, the channel density is reduced. The turning on of the parasitic PMOS has a potential-clamping effect on the NMOS channel, so that the saturation current can be reduced and a wider short-circuit safe operating area (SCSOA) can be obtained.

Three-dimensional carrier stored trench IGBT and manufacturing method thereof

A bidirectional conduction trench gate power MOS device and a manufacturing method thereof are provided. A gate electrode, a source electrode and a drain electrode are formed on a surface of a silicon wafer to realize a bidirectional conduction and bidirectional blocking power MOS device used in an application environment such as lithium battery BMS protection. A device structure of the bidirectional conduction trench gate power MOS device has advantages compared with double-transistor series connection used in a conventional BMS and other structures for realizing a bidirectional conduction: firstly, the bidirectional conduction trench gate power MOS device needs to occupy half or less area compared with a conventional mode, improving a degree of integration; secondly, the device structure has a simple manufacturing process and a low manufacturing cost reducing manufacturing problems; thirdly, the drain electrode and the source electrode of the device structure are exchanged to realize a symmetrical structure.

Bidirectional conduction trench gate power MOS device and manufacturing method thereof

The present disclosure provides a hetero-integrated terahertz low-noise miniaturized image frequency rejection transceiver front-end, including an intermediate frequency circuit and a terahertz circuit arranged up and down, where the terahertz circuit includes a local oscillator frequency tripler, a 135° 3 dB filter coupler, a radio frequency waveguide power divider, and two quartz hetero-integrated subharmonic mixers; resonant cavities of an input unit, a first output unit, an isolation unit, and a second output unit of the 135° 3 dB filter coupler are sequentially coupled through resonant grooves to form a ring structure, a cavity length of the resonant cavity of the input unit is twice that of the resonant cavities of the other three units, and an electrical length of a waveguide of the first output unit is 45° different from that of a waveguide of the second output unit.

Hetero-integrated terahertz low-noise miniaturized image frequency rejection transceiver front-end

The present disclosure provides a GaAs monolithic integrated terahertz low-noise communication system transceiver front-end, including an intermediate frequency circuit and a terahertz circuit. The terahertz circuit includes a local oscillator frequency tripler, a local oscillator unidirectional 3 dB filter coupler, a radio frequency 180° filter coupler, and two terahertz GaAs monolithic integrated subharmonic mixers. The local oscillator unidirectional 3 dB filter coupler and the radio frequency 180° filter coupler each include one ring-cylindrical resonant cavity and four rectangular waveguides. The ring-cylindrical resonant cavity is divided into four rectangular waveguides which are correspondingly connected to the four sector-annular resonant cavities, respectively. The present disclosure suppresses the local oscillator noise by adopting a local oscillator unidirectional 3 dB filter coupler and a radio frequency 180° filter coupler with both coupling and filtering functions, thereby achieving a low local oscillator noise transceiver front-end.

GaAs monolithic integrated terahertz low-noise communication system transceiver front-end

A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.

Multi-level gate driver applied to SiC MOSFET

The present invention relates to dental medical instruments, and specifically discloses an automatic grinding drill device for oral caries, including a mounting frame. Two retainers are arranged on the mounting frame, the bottom of the mounting frame is connected with a support plate through drive assemblies, a drill bit assembly is arranged at the bottom of the support plate, and a visual recognition module is also arranged on the support plate. The present invention has the advantage that the retainers keep a real-time relative static state with teeth of a patient during use, needing no frequent correction, so that operation steps are simplified.

Automatic grinding drill device for oral caries

A terahertz full-duplex co-local oscillator solid-state front-end transmitting circuit is disclosed, which belongs to the technical field of terahertz communication. The overall structure of the solid-state front-end transmitting circuit adopts a new system, wherein the circuit comprises two branches that are parallel and driven by a local oscillator source. A branched waveguide directional coupler is configured to output two driving signals provided by the same local oscillator source respectively to two branch circuits with required powers. Two transmission signals generated from the two branches are combined into one signal for transmission through an orthogonal mode coupled duplexer, so as to fulfill the construction of a full-duplex co-local oscillator solid-state front-end transmission circuit.

Terahertz full-duplex co-local oscillator solid-state front-end transmitting circuit

The present invention belongs to the field of animal gas anesthesia, and provides a quantitative and precise gas anesthesia method and device for experimental animals. The quantitative and precise gas anesthesia device for experimental animals includes an anesthetic fluid tank, a drainage tube, catheters, closed animal anesthetic tanks, and a recycling container, where anesthetic fluid is put into the anesthetic fluid tank, the bottom of the anesthetic fluid tank is connected to an inlet of the drainage tube, a set of holes are evenly arranged in the drainage tube, each hole is connected to an inlet of each catheter, and outlets of the catheters extend into the closed animal anesthetic tanks.

Quantitative and precise gas anesthesia method and device for experimental animals

A lateral power semiconductor device includes a first type doping substrate at a bottom of the lateral power semiconductor device, a second type doping drift region, a second type heavy doping drain, a first type doping body; a first type heavy doping body contact and a second type heavy doping source, where dielectric layers are on a right side of the second type heavy doping source; the dielectric layers are arranged at intervals in a longitudinal direction in the first type doping body, and between adjacent dielectric layers in the longitudinal direction is the first type doping body; and a polysilicon is surrounded by the dielectric layer at least on a right side. Compared with conventional trench devices, the lateral power semiconductor device introduces a lateral channel, to increase a current density, thereby realizing a smaller channel on-resistance.

Lateral power semiconductor device

An SOI lateral homogenization field high voltage power semiconductor device, and a manufacturing method and application thereof are provided. The device includes a type I conductive semiconductor substrate, a type II conductive drift region, a type I field clamped layer, type I and type II conductive well regions, the first dielectric oxide layer forming a field oxide layer, the second dielectric oxide layer forming a gate oxide layer, a type II conductive buried dielectric layer, a type II conductive source heavily doped region, a type II conductive drain heavily doped region. The first dielectric oxide layer and the floating field plate polysilicon electrodes form a vertical floating field plate distributed throughout the type II conductive drift region to form a vertical floating equipotential field plate array. When the device is in on-state, high doping concentration can be realized by the full-region depletion effect form the vertical field plate arrays.

SOI lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof

A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein Cof the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating Ccaused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.

Power semiconductor device

Growing community of inventors

Chengdu, China

Bo Zhang