Globalfoundries Singapore Pte. Ltd.

Globalfoundries Inc.

Chartered Semiconductor Manufacturing Ltd (corporation)

Institute of Microelectronics

Bo Yu

Shaoqiang Zhang

Purakh Raj Verma

Rui Tze Toh

Mei Sheng Zhou

Guan Huei See

Chim Seng Seet

Benfu Lin

Raj Verma Purakh

Shao-Fu S Chu

My The Doan

Dina H Triyoso

Kin Wai Tang

Zeng Wang

Shyam Parthasarathy

Jian Hui Ye

Chester Leung

Mark Hatzilambrou

Yuzhan Wang

Kouassi Sebastien Kouassi

Qing Hua Zhong

Yin Qian

Eric Johnson

Wensheng Deng

Tao Jiang

According to various embodiments, an integrated circuit may include an upper inter-level dielectric (ILD) layer, a lower ILD layer, and an interlayer arranged between the upper ILD layer and the lower ILD layer. The integrated circuit may further include a capacitor device and a resistor device. The capacitor device may include a top plate disposed in a first region of the interlayer and a bottom plate disposed in the lower ILD layer. The resistor device may include a resistive element and a plurality of vias disposed in a second region of the interlayer. The plurality of vias may extend from the resistive element to the lower ILD layer. A distance between the top plate and the lower ILD layer may be at least substantially equal to a height of each via of the plurality of vias.

Integrated circuits and methods of forming integrated circuits

A device may include a semiconductor-on-insulator (SOI) structure that may include a substrate, an insulator layer over the substrate, and a semiconductor layer over the insulator layer. The semiconductor layer may include a first conductivity region and a second conductivity region at least partially arranged within the semiconductor layer. The device may further include a gate structure arranged over the semiconductor layer and between the first conductivity region and the second conductivity region; a first conductor element arranged through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate; a second conductor element arranged to electrically contact the gate structure; and a conducting member connecting the first conductor element and the second conductor element to electrically couple the first conductor element and the second conductor element.

Semiconductor device having conducting member for electrically coupling gate structure to underlying substrate of SOI structure

Methods for fabricating integrated circuits are provided. In one example, a method includes depositing an ILD layer overlying a SOI substrate including a device structure and an isolation structure. The device structure is disposed on a semiconductor layer of the SOI substrate and includes a metal silicide region and the isolation structure extends through the semiconductor layer to a buried insulator layer of the SOI substrate. A patterned mask is used for etching through the ILD layer and forming a device contact opening that exposes the metal silicide region and a substrate contact opening that exposes the isolation structure. A device contact is formed in the device contact opening. The isolation structure and the buried insulator layer are etched through to extend the substrate contact opening to a support substrate of the SOI substrate. A substrate contact is formed in the substrate contact opening.

Methods for fabricating integrated circuits including substrate contacts

Methods of forming a SOI PA and RF switch device having a thin BOX layer in the PA power cell region and a thick metal layer directly under the thin BOX layer and the resulting device are provided. Embodiments include providing a SOI structure having a substrate, BOX, device and metallization layers; bonding a handling layer to the metallization layer; removing the substrate; forming a passivation oxide layer over the BOX; forming first and second trenches through the passivation, BOX, and device layers down to the metallization layer; forming a third trench through the passivation layer and a portion of the BOX above a PA power cell region of the SOI structure, a thin portion of the BOX remaining; forming a first backside contact in the first trench; and forming a second backside contact in the second and third trenches and over a portion of the passivation oxide layer.

Heat dissipation and series resistance reduction of PA and RF switch in SLT by backside thick metal

Methods for fabricating MIM capacitors with low VCC or decoupling and analog/RF capacitors on a single chip and the resulting devices are provided. Embodiments include forming: first and second metal lines in a substrate; a first electrode over, but insulated from, the first metal line; a first high-k dielectric layer on the first electrode, the first high-k dielectric layer having a coefficient &#x3b1;; a second electrode on the first high-k dielectric layer and over a portion of the first electrode; a second high-k dielectric layer on the second electrode, the second high-k dielectric layer having a coefficient &#x3b1;' opposite in polarity but substantially equal in magnitude to &#x3b1;; a third electrode on the second high-k dielectric layer over the entire first electrode; and a metal-filled via through a dielectric layer down to the first metal line, and a metal-filled via through the dielectric layer down to the second metal line.

Method of fabricating a MIM capacitor with minimal voltage coefficient and a decoupling MIM capacitor and analog/RF MIM capacitor on the same chip with high-K dielectrics

Devices and methods for forming a device are presented. The method includes providing a substrate having at least a first region and a second region prepared with isolation regions. The first region is referred to as a chip guarding area and the second region defines a chip region of which at least one transistor is to be formed. The substrate includes a top surface layer, a support substrate and an insulator layer in between them. A transistor is formed in the second region and a substrate contact structure is formed in the first region. The substrate contact structure passes through at least the top surface layer, insulator layer and isolation region and contacts a doped region in the support substrate. The substrate contact structure is connected to at least one conductive line with a desired potential to prevent charging of the support substrate at system level.

Grounding of silicon-on-insulator structure

A method of integrated circuit component integration in copper interconnects, including the following steps of the first embodiment. A wafer is provided having an exposed top-most planar copper interconnect. The wafer being divided into one or more areas selected from the group consisting of: a spiral inductor area having an exposed planar copper interconnect bottom half of a stacked spiral inductor; a MIM capacitor area having an exposed planar copper interconnect bottom plate and an exposed planar copper interconnect contact point of a MIM capacitor; and a precision resistor area having a two exposed planar copper interconnect routing points of a precision resistor. A spiral inductor is formed within the spiral inductor area; a MIM capacitor is formed within the MIM capacitor area; and a precision resistor is formed within the precision resistor area.

Single damascene method for RF IC passive component integration in copper interconnect process

A method for forming insulator filled, shallow trench isolation regions, with rounded corners, has been developed. The process features the use of a polymer coated opening, in an insulator layer, used as a mask to define the shallow trench region in silicon. After completion of the shallow trench formation the polymer spacers are removed, exposing a region of unetched semiconductor, that had been protected by the polymer spacers, during the shallow trench dry etching procedure. The sharp corner, at the intersection between the shallow trench and the unetched region of semiconductor, is then converted to a rounded corner, via thermal oxidation of exposed silicon surfaces. The polymer spacers also eliminate the top corner wraparound.

Use of polymer spacers for the fabrication of shallow trench isolation

Growing community of inventors

Singapore, Singapore

Bo Yu