Realtek Semiconductor Inc.

Lextar Electronics Corporation

Bo-Yu Chen

Yao-Chia Liu

Leaf Chen

Tzu-Hung Chou

Po-Hung Tsou

An-Ming Lee

Ming-Hui Tung

Li-Jun Gu

Guan-Yu Chen

Kai-Yuan Yin

Wen-Bin Wu

A USB switching circuit includes a first multiplexer, a second multiplexer coupled with the first multiplexer through transmission paths, and a voltage regulation circuit coupled with the first and second multiplexers. The first multiplexer distributes first data signals to the transmission paths according to first control signals. The second multiplexer distributes a second data signal to the transmission paths according to second control signals. The voltage regulation circuit sets a maximum voltage and a minimum voltage of the first data signals to corresponding to a common voltage. The maximum voltage of the first data signals is not higher than a maximum voltage of the second control signals, or the minimum voltage of the first data signals is not lower than a minimum voltage of the second control signals. The first data signals and the second data signal are generated according to different communication protocols.

USB switching circuit and electronic apparatus having the same

The present disclosure provides a clock data recovery apparatus. The clock data recovery apparatus includes a phase detection circuit, a digital filter, a phase-interpolating circuit and an oscillator circuit. The phase detection circuit receives and samples a data signal according to multiple reference clock signals having different phases, to generate a phase detection result. The digital filter performs accumulation on the phase detection result, to generate a phase-adjusting signal. The phase interpolator circuit performs phase adjustment on a source clock signal according to the phase-adjusting signal, in order to generate an injection clock signal. The oscillator circuit generates the reference clock signals according to the injection clock signal, in which the phases of the reference clock signals follow the phase of the injection clock signal.

Clock data recovery apparatus and clock data recovery method

An equalizer circuit includes a first arithmetic circuit, a second arithmetic circuit, a data sampling circuit, and an edge sampling circuit. The first arithmetic circuit is configured to compensate an equalization sequence by secondary feedback sequences to output a first added sequence. The second arithmetic circuit is configured to compensate the first added sequence by a primary feedback sequence to output a second added sequence. The data sampling circuit samples, according to data clock, the second added sequence to output a primary sequence, and gains the primary sequence to output the primary feedback sequence. The data sampling circuit sequentially samples, according to the data clock, the primary sequence to output secondary sequences. The data sampling circuit gains the corresponding secondary sequences to output the secondary feedback sequences. The edge sampling circuit is configured to sequentially sample, according to an edge clock, the first added sequence to output an edge sequence.

Equalizer circuit

A timing control device and a timing control method for a high frequency signal system, the timing control method respectively control trigger points of reset signals, and process the controlled reset signals and clock signals to obtain a signal group with having an absolute timing relationship.

Timing control device and method for high frequency signal system

A clock circuit has a clock input terminal, a first clock output terminal, and a second clock output terminal. The clock circuit includes a pulse width adjustment module, a sampling module, a comparing module, and a differential signal converting module. A differential input terminal is electrically connected to a pulse width output terminal of the pulse width adjustment module. A positive differential signal output terminal and a negative differential signal output terminal are electrically connected to the first clock output terminal of the clock circuit and the second clock output terminal to output two clock signals with a phase difference of 180 degrees, respectively. A second input terminal of the sampling module is electrically connected to the second clock output terminal.

Clock circuit having a pulse width adjustment module

A differential switch circuit includes: a first transistor having a first terminal coupled with a first input terminal, a second terminal coupled with a first output terminal, and a control terminal coupled with a switch signal receiving terminal; a second transistor having a first terminal coupled with a second input terminal, a second terminal coupled with a second output terminal, and a control terminal coupled with the switch signal receiving terminal; a central switch element positioned between the control terminals of the first and second transistors; and a switch element control circuit for controlling the central switch element based on a switch signal. When the switch signal turns on the first and second transistors, the switch element control circuit turns off the central switch element, and when the switch signal turns off the first and second transistors, the switch element control circuit turns on the central switch element.

Differential switch circuit

A light emitting diode structure is provided. The light emitting diode structure includes a substrate, a light emitting multi-layer structure, a first current blocking layer, a first current spreading layer, a second current blocking layer and a second current spreading layer. The light emitting multi-layer structure is formed on the substrate by way of stacking. The first current blocking layer is formed on part of the light emitting multi-layer structure. The first current spreading layer covers the first current blocking layer and the light emitting multi-layer structure. The second current blocking layer is formed on part of the first current spreading layer. An orthogonal projection of the second current blocking layer is disposed in an orthogonal projection of the first current blocking layer. The second current spreading layer covers the second current blocking layer and the first current spreading layer.

Growing community of inventors

Hsinchu, Taiwan

Bo-Yu Chen