Ambarella International LP

Huawei Digital Power Technologies Co., Ltd.

Qualcomm Incorporated

Teradyne (Asia) Pte. Ltd.

Forqaly Medical (Shanghai) Co., Ltd.

Bo Yu

Bo Li

Nan Zhang

Yu Zhang

Yanzhong Zhang

Xudong Wang

Liangliang Wang

Wenhai Gao

Yongjun Xu

Yu Peng

Jun Liu

Yang Xu

Junjie Li

Zhong Wang

He Zhou

Shijiang Yu

Jianshan Li

Shengjie Zhang

Hongmiao Fang

Jinxiang Zhan

Sicong Lyu

Dongliang Lu

Qiwen Zhen

Min Nie

Yi Hou

Siqiang Jia

Jun Tang

Yongpeng Mu

A first input end of a first inverter is connected to a second end of a direct current positive bus, and a second input end of the first inverter is connected to a second end of a neutral bus. A first input end of a second inverter is connected to the second end of the neutral bus, and a second input end of the second inverter is connected to a second end of a direct current negative bus. A controller is configured to control, in startup and shutdown processes, a voltage to ground of the direct current positive bus, a voltage to ground of the direct current negative bus, and a voltage to ground of the neutral bus each to be less than or equal to a preset voltage threshold, to ensure personal safety and device safety.

Photovoltaic system, power supply system, and control method

The present disclosure relates to methods and apparatus for display processing. Aspects of the present disclosure can communicate an image to multiple display panels, where the multiple display panels include a first display panel and a second display panel. Further, aspects of the present disclosure can divide the image between the first display panel and the second display panel. Additionally, aspects of the present disclosure can scale at least one of a first portion of the image or a second portion of the image to at least one of the first display panel and the second display panel. Aspects of the present disclosure can also display at least one of the scaled first portion of the image or the scaled second portion of the image on at least one of the first display panel or the second display panel.

Methods and apparatus for partial display of frame buffers

Device under test (DUT) simulation equipment includes: a first circuit board including a first field programmable gate array (FPGA); a second circuit board including a processor; and a power distribution board, wherein the first circuit board is connected to the power distribution board, and the power of the first circuit board is supplied by the power distribution board, wherein the second circuit board is connected to the power distribution board, and the power of the second circuit board is supplied by the power distribution board, wherein when the DUT simulation equipment is connected to a tester to perform testing, the DUT simulation equipment simulates the performance of a DUT providing a response signal after receiving a test signal from the tester, and wherein, in the DUT simulation equipment, only the first circuit board receives the test signal from the tester, and the second circuit board controls the first circuit board by means of a control signal.

Device under test simulation equipment

An apparatus comprises an interface and a processor. The interface may be configured to receive pixel data. The processor may be configured to (i) process the pixel data arranged as video frames, (ii) decompose each of the video frames comprising a high-resolution two-dimensional (2D) image into a plurality of 2D sub-images using a decomposition offset, (iii) decompose each of the video frames comprising a high-resolution depth map image into a plurality of depth map sub-images using the decomposition offset, (iv) calculate a respective alignment matrix for each of the plurality of 2D sub-images and a corresponding one of the plurality of depth map sub-images using the decomposition offset, (v) perform matrix operations on the plurality of 2D sub-images and the plurality of depth map sub-images using the respective alignment matrices to obtain a plurality of aligned 2D sub-images and depth map sub-images, (v) determine projection coordinates and depth values of the plurality of aligned 2D sub-images and depth map sub-images based on the high-resolution 2D image, and (vi) generate an aligned high-resolution depth map using the projection coordinates and depth values.

Accelerated alignment of high-resolution image and depth map for low-bit-width floating-point representation

An apparatus comprising an interface, a light projector and a processor. The interface may be configured to receive pixel data. The light projector may be configured to generate a structured light pattern. The processor may be configured to process the pixel data arranged as video frames and generate disparity and depth maps. The processor may comprise convolutional neural network hardware that may arrange reference images into a tensor, perform logical operations on one of the video frames in a depth direction of the tensor to generate a tensor of feature maps of the video frames, use a convolution to reduce an amount of calculations performed in the depth direction of the tensor of feature maps, perform convolution filtering on the tensor of the feature maps, determine an index map location, and search lookup data based on the index map location to determine the disparity and depth maps.

Accelerating speckle image block matching using convolution techniques

An apparatus comprising an interface, a structured light projector and a processor. The interface may receive pixel data. The structured light projector may generate a structured light pattern. The processor may process the pixel data arranged as video frames, perform operations using a convolutional neural network to determine a binarization result and an offset value and generate disparity and depth maps in response to the video frames, the structured light pattern, the binarization result, the offset value and a removal of error points. The convolutional neural network may perform a partial block summation to generate a convolution result, compare the convolution result to a speckle value to determine the offset value, generate an adaptive result in response to performing a convolution operation, compare the video frames to the adaptive result to generate the binarization result for the video frames, and remove the error points from the binarization result.

Adding an adaptive offset term using convolution techniques to a local adaptive binarization expression

A photovoltaic energy system and a method for detecting a ground insulation impedance, improve accuracy of detecting a ground insulation impedance after one or more conversion circuits are connected in parallel. The photovoltaic energy system includes one or more conversion circuits and a detection circuit. The detection circuit includes an alternating current signal source and a sampling resistor that are connected in series, a first sampling circuit, and a control circuit. The control circuit is configured to control the alternating current signal source to output harmonic signals of a first frequency and a second frequency. The first sampling circuit is configured to: when the alternating current signal source outputs the harmonic signal of the first frequency, collect a voltage at both terminals of the sampling resistor to obtain a first voltage.

Photovoltaic energy system and method for detecting ground insulation impedance

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Shanghai, China

Bo Yu