Skhynix Inc.

Hynix Semiconductor Inc.

Bo-Yeun Kim

Seok-Cheol Yoon

Ji-Eun Jang

Jae-Il Kim

Jae-Boum Park

Saeng-Hwan Kim

Chul-Moon Jung

Kyoung-Chul Jang

A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address corresponding to a first external signal that is inputted at a random time, and a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation.

Address storage circuit and memory and memory system including the same

A semiconductor device may include a common coupling block suitable for coupling a plurality of first data lines to a plurality of second data lines in response to a common control signal, which is activated regardless of a data bandwidth option mode, a first coupling block suitable for coupling a part of the plurality of second data lines to a part of a plurality of third data lines in response to a first operation control signal, a second coupling block suitable for coupling the other part of the plurality of second data lines to the other part of the plurality of third data lines in response to a second operation control signal, and a control block suitable for activating one or more of the first and second operation control signals based on the data bandwidth option mode, during a data input/output operation.

Semiconductor device and method of driving the same

A memory includes a plurality of word lines each coupled to one or more memory cells, an address storage unit suitable for storing an address of a word line selected for access by a control unit among the plurality of word lines at a first time point; and the control unit suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command, refreshing one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every Nth application of the refresh command where N is a natural number and selecting one or more of the plurality of word lines for access, wherein the first time point is included in time section other than a refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command.

Memory and memory system including the same

A memory may include a plurality of word lines, one or more redundancy word lines for replacing one or more word lines among the plurality of word lines, a target address generation unit suitable for generating one or more target addresses using a stored address, and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, refreshing a word line selected based on the target address when the refresh command is inputted M times, and refreshing the one or more redundancy word lines whenever the refresh command is inputted N times, wherein the M and N are natural numbers.

A memory may include a plurality of word lines coupled to one or more memory cells; a target address generation unit suitable for generating one or more target addresses using a stored address; and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, and refreshing a word line corresponding to the target address in response to the refresh command at a random time.

Memory performing target refresh operation and memory system including the same

A semiconductor device includes conducting lines of a first group and a second group arranged in parallel, a plurality of first internal elements respectively coupled to the conducting lines of the first group and the second group and a plurality of first contact pads arranged between and along the conducting lines of the first group and the second groups, wherein at least a part of the plurality of first contact pads are respectively coupled to control terminals of the plurality of first internal elements, and the part of the plurality of first internal elements receive a plurality of first control signals through corresponding control terminals, respectively.

Semiconductor device

A semiconductor device includes a plurality of cell blocks activated in response to a plurality of selection signals, respectively, a pre-selection signal generator configured to generate a plurality of pre-selection signals corresponding to the cell blocks, respectively, and activate at least two of the pre-selection signals by decoding addresses in a multi-test mode, a selection signal controller configured to selectively activate the plurality of selection signals in response to the plurality pre-selection signals and control active periods of the activated selection signals so as not to overlap, and a decision circuit configured to decide whether or not the cell blocks activated in response to the activated selection signals are repaired in response to stored repair information and the plurality of selection signals.

Semiconductor device and testing method thereof

A semiconductor memory device includes a reset signal generating unit configured to generate a reset control signal by delaying a column command signal by an amount of time varying proportional to an operational frequency. A pulse width determination unit is configured to determine a pulse width of a column selection signal in response to the column command signal and the reset control signal. An address decoding unit is configured to generate the column selection signal corresponding to a corresponding column address in response to an output signal of the pulse width determination unit.

Semiconductor memory device with pulse width determination

A test mode control circuit of a semiconductor memory device includes an input unit configured to input test mode data for at least one of a plurality of test modes, and a test mode controlling unit configured to enable/disable a test mode according to the number of inputs of the test mode data.

Test mode control circuit and method for using the same in semiconductor memory device

Semiconductor memory device and parallel test method of the same. The test includes writing data into multiple memory banks simultaneously, reading the data from a portion of the memory banks, compressing the read data and outputting the compressed data to the outside of a chip.

Semiconductor memory device and parallel test method of the same

A semiconductor memory device includes a clock period detector, a column address enable signal generator, and a multiplexing circuit. The clock period detector detects a period of an external clock in response to a pulse width information signal having a pulse width corresponding to that of the external clock. The column address enable signal generator generates a column address enable signal activated in response to a column access signal. The multiplexing circuit multiplexes points of time of inactivation of the column access signal in response to the detected signal outputted from the clock period detector.

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Gyeonggi-do, South Korea

Bo-Yeun Kim