Apple Inc.

Hitachi, Ltd.

Nvidia Corporation

Apple Ine.

Bo Yang

Yanzhu Ye

Panitarn Chongfuangprinya

Vijay M Bettada

Xiang Lu

Bibo Li

Masanori Abe

Karthik Manickam

Andrew J Copperhall

Hopil Bae

Derek Keith Shaeffer

Shawn Searles

Vincent R Von Kaenel

Mahdi Farrokh Baroughi

Henry C Jen

Amit D Sanghani

Jay B Fletcher

Yasushi Tomita

Hubert Attah

Sumito Tobe

Olivier Girard

Nir Dahan

Vasu P Ganti

Sagar Nataraj

Natsuhiko Futamura

Anthony Hoang

Brijesh Tripathi

Mohammad Bagher Vahid Far

Michael R Seningen

Erik P Machnicki

Toshinari Takayanagi

Jun Yamazaki

Jung Wook Cho

Eric G Smith

Hsiu-Khuern Tang

Antonietta Oliva

Matthias Knoth

Karthikeyan Natarajan

Kiran Kattel

Khaled M Alashmouny

Alex Wang

Wenlong Wei

Jian Gao

Shriram Vijayakumar

An apparatus includes a first set of scan-enabled flip-flop circuits may be configured to shift a scan-chain pattern from a first test input node to a first test output node using a first clock signal. A particular lockup latch may be coupled to the first test output node and to a second test input node. This particular lockup latch may be configured to, when enabled, delay propagation of the scan-chain pattern from the first test output node to the second test input node. A second set of scan-enabled flip-flop circuits may be configured to shift the scan-chain pattern from the second test input node to a second test output node using a second clock signal, different from the first clock signal. A control circuit may be configured to determine whether to enable the particular lockup latch using a particular scan test signal.

Scan data transfer circuits for multi-die chip testing

A method for visualization of an end device. The method may include setting an object display limit on a display map, the display map displaying a plurality of objects, and wherein each of the plurality of objects is assigned a priority status; receiving data from the end device; classifying the data and assigning priority status to an object with the data, wherein the object is added to the plurality of objects; and displaying the plurality of objects based on priority status and the object display limit.

Behind-the-meter devices visualization method and computing system

An apparatus includes a plurality of circuit blocks, a plurality of scan-enabled flip-flop circuits, and a plurality of scan signature circuits. The plurality of scan-enabled flip-flop circuits may be coupled in a sequential manner across the plurality of circuit blocks, and be configured to shift a scan chain test signal from a test input interface to a test output interface. The plurality of scan signature circuits may be coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and be configured to, in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits. The plurality of scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface.

Scan chain analysis using predefined capture signature

Example implementations described herein provide systems and methods for visualization of power distribution feeder networks. The systems and methods involve setting a limit of objects of the power distribution network to be displayed on a map, the objects comprising at least nodes and links between the nodes, the links comprising at least conductive lines; when the total number of the objects exceeds a limit, selecting one or more subsets of the conductive lines based on one or more conditions related to the conductive lines; and generating a first visualization displaying the map comprising a subset of the objects including the one or more subsets of the conductive lines, wherein a number of displayed objects is less than or equal to the limit.

Distribution system visualization method and computing system

A voltage regulator circuit included in a computer system may generate a voltage level on a power supply signal using a source power supply signal and based initial values of one or more operation parameters derived from wafer-level test data. One or more operation characteristics of the voltage regulator circuit may be sampled, by a measurement circuit, at multiple time points to generated measurement data. A control circuit may adapt operation of the voltage regulator circuit based on the measurement data.

Computer system power monitoring

Example implementations described herein are directed to managing the operation of a plurality of electric vehicles (EVs) for transportation service, power system operating reserve service and operation planning, which is utilized to determine whether to use each EV for transportation travel or power system operating reserve supply for a given time period and location. Such management allows for the increase of the total operation value by transportation travel and power system operation reserve supply.

Electric vehicles operation management equipment

Example implementations described herein involve a multi-layer hybrid model power generation prediction method and computing system. The example implementations described herein are configured to predict power generation that can be utilized for short-term planning by utilities to optimize operation planning to ensure economic and stable operation of the electricity.

Multi-layer hybrid model power generation prediction method and computing system

Example implementations described herein involve a hybrid spatial-temporal event probability prediction method and system configured to predict spatial-temporal event probability that can be utilized for short term planning. For systems such as utility systems that manage multiple locations over time, the example implementations utilize both a spatial model and a temporal model to create a hybrid spatial-temporal model that accounts for data taken over time as well as data across the locations to more accurately forecast the probability of an event occurrence over a period of time.

Hybrid spatial-temporal event probability prediction method

The multi-time scale battery energy/storage system (BES) management framework proposed in the present disclosure can be used for day-ahead capacity scheduling and real-time BES operation control in the latest performance-based frequency regulation market. This multi-time scale BES management framework includes three control layers: long-term battery performance planning layer, day-ahead regulation capacity scheduling layer, real-time battery operation control layer. These three layers will coordinate with each other, and operate at different time scales.

Multi-time scale energy storage management framework for performance-based frequency regulation (FR) market

Methods and systems for testing a display having an array of microdrivers arranged in multiple of rows and columns including setting a testing mode of a microdriver of the array of microdrivers using multiple pins of the microdriver that are used in scanning or operation modes of the microdriver. The microdriver is configured to light one or more connected micro light emitting diode pixels coupled to the microdriver during the testing mode. Testing also includes operating the microdriver in the testing mode and determining functionality of the one or more connected micro light emitting diode pixels or the microdriver based on the testing mode.

Micro light emitting diode testing

The present techniques are capable of identifying and pinpointing defective microdrivers and/or row/column drivers either before or after any &#x3bc;LEDs have been placed on the display. Using the architectures described herein, test data may be delivered in a parallel fashion to the drivers from support circuitry, such as a timing controller and/or a main board, and outputs based on the test data may be similarly delivered back to the support circuitry do determine which drivers are defective. This yields access to the output of every microdriver and row drier, thus enabling the identification of specific defective elements.

Techniques for testing electrically configurable digital displays, and associated display architecture

Design-for-test (DFT) architectures, and methods of testing an array of chips, which may be identical, are described. In an embodiment, a comparison circuit includes a plurality of comparators to compare scan-data out (SDO) data streams with an expected data stream and transmit a compared data stream that is indicated of whether or not an error exists in any of the SDO data streams.

Test-response comparison circuit and scan data transfer scheme in a DFT architecture for micro LED based display panels

An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

Power droop measurements using analog-to-digital converter during testing

A hardware assisted scheme for testing IC memories using scan circuitry is disclosed. An IC includes a memory implemented thereon and a chain of serially-coupled scan elements to enable the inputting of test vectors. The scan elements include first and second subsets forming write and read address registers, respectively, a first control flop, and a second control flop. During a launch cycle of a test operation, a first address loaded into the write address register is provided to a write address decoder to effect a write operation. Also responsive to the launch cycle, the first control flop is configured to cause the first address to be provided to the read address register, while the second control flop causes data to be written into the memory. During a capture cycle, the first address is provided to a read address decoder and the second control flop causes a read of data therefrom.

Hardware assisted scheme for testing memories using scan

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Santa Clara, CA, United States of America

Bo Yang