International Rectifier Corporation

Qualcomm Incorporated

Infineon Technologies Americas Corp.

Bo Yang

Jason Zhang

Michael A Briere

Chuan Cheah

Kenneth Charles Barnett

Ashok Swaminathan

Nitz Saputra

Kunzhong Hu

Harish S Muthali

Osama Elhadidy

Peter Gazzerro

Methods and apparatus for filtering a signal using a current-mode filter circuit implementing source degeneration. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor comprising a drain coupled to the input node; a second transistor comprising a drain coupled to the output node and comprising a gate coupled to a gate of the first transistor; a capacitive element coupled between the drain of the first transistor and the power supply node; a first resistive element coupled between the drain and the gate of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

Wideband current-mode low-pass filter circuits

A passive mixer may include an output coupled to a next stage circuit. The output may be coupled to baseband inputs via first switches. The passive mixer may further include a tunable capacitor bank. The tunable capacitor bank may be coupled via second switches to the baseband inputs.

Passive mixer

Disclosed is a buck converter for converting a high voltage at the input of the buck converter to a low voltage at the output of the buck converter. The buck converter includes a control circuitry configured to control a duty cycle of a control switch, the control switch being interposed between the input and the output of the buck converter. A synchronous switch is interposed between the output and ground. The control switch and the synchronous switch comprise depletion-mode III-nitride transistors. In one embodiment, at least one of the control switch and the synchronous switches comprises a depletion-mode GaN HEMT. The buck converter further includes protection circuitry configured to disable current conduction through the control switch while the control circuitry is not powered up.

DC/DC converter with III-nitride switches

DC/DC converter with depletion-mode III-nitride switches

An integrated circuit for a half cycle delay locked loop is disclosed. The integrated circuit includes an input node coupled to an oscillator having a clock cycle of M. The integrated circuit also includes N delay elements outputting N different phase-shifted signals, where a total delay introduced by the N delay elements is M/2. The integrated circuit also includes a plurality of inverters, each coupled to an output of one of the N delay elements, where the plurality is less than N. The integrated circuit also includes a phase detector coupled to the input node and an inverted Nth phase-shifted signal. The integrated circuit also includes a charge pump coupled to the phase detector and the delay elements.

Half cycle delay locked loop

A phase locked loop apparatus includes an oscillator, a variable capacitance device, a selectable capacitance device, and a capacitance controller that is configured to provide a control signal to the selectable capacitance device. The selectable capacitance device is connected to the oscillator and is responsive to the control signal such that the selectable capacitance device has a first capacitance at a first control signal value and a second capacitance at a second control signal value. The capacitance controller only selects either the first capacitance or the second capacitance by providing a control signal that has the first control signal value to select the first capacitance and having the second control signal value to select the second capacitance.

Phase locked loop apparatus with selectable capacitance device

A circuit comprising a gate driver including first and second switching stages for driving respective sync and control switches, at least one of which is a normally ON depletion mode device, and another circuit connected to the first and second switching stages and including first and second circuits. The first circuit is coupled to the first switching stage and to the sync switch, the first switching stage having a first state wherein the sync switch is on, and a second state wherein a first bias voltage is switched to the gate of the sync switch to turn it off. The second circuit has a first state wherein the control switch is on when the sync switch is off, and a second state wherein the control switch is switched off when the sync switch is on by switching a second bias voltage to the gate of the control switch.

Gate driver in buck converters

A multichip module defining a dc to dc converter employs a monolithic chip containing at least two III-nitride switches (a monolithic CSC chip) mounted on a conductive lead frame. The CSC chip is copacked with an IC driver for the switches and with the necessary passives. The module defines a buck converter; a boost converter, a buck boost converter, a forward converter and a flyback converter. The drain, source and gate pads of the monolithic CSC chip are connected to a lead frame by solder or epoxy or by bumping attach and a conductive connector or wire bonds connect the switch terminal to lead frame.

Package for monolithic compound semiconductor (CSC) devices for DC to DC converters

A buck converter circuit is disclosed in which one or both of the control switch and the synchronous switch are III-nitride-based depletion mode. An enhancement mode switch is connected with one or both of the III-nitride based switches and operated to prevent conduction of current by the III-nitride based switch until all biases are established for proper operation.

DC/DC converter including a depletion mode power switch

Gate driving scheme for depletion mode devices in buck converters

A method of improving the operation of a synchronous rectifier circuit which includes a switching transistor and synchronous transistor, by providing an operatively effective value of inductance in the current path of the synchronous transistor; which is shared by the control terminal circuit path of the transistor and by selecting a synchronous transistor having a low resistance to a control signal provided at the control terminal, as well as improved synchronous rectifier circuits designed according to the method. When the transistors are MOSFETs, the inductance provided is preferably a purely parasitic common source inductance in the range of about 2 nH to about 3 nH. The synchronous transistor exhibits a low value of gate resistance to facilitate fast energy exchange between the common source inductance and the gate-source capacitance.

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San Diego, CA, United States of America

Bo Yang