Industrial Technology Research Institute

Bo-Wen Wang

Shang-Li Chen

Jun-Ren Shih

Jan-Ruei Lin

A shift-register unit. The first transistor includes a first source/drain coupled to a first terminal, a second source/drain, and a first gate coupled to a reset signal to stop the shift-register unit outputting a pulse signal. The second transistor includes a third source/drain coupled to the second source/drain, a fourth source/drain coupled to a second terminal, and a second gate coupled to a setting signal to initial the shift-register unit. The third transistor includes a fifth source/drain coupled to an output terminal, a third gate coupled to the second source/drain and a sixth source/drain coupled to a clock signal to start outputting the pulse signal. The fourth transistor includes a seventh source/drain coupled to the first terminal, an eighth source/drain coupled to the output terminal and a fourth gate coupled to a refresh signal to set a voltage level of the shift-register unit in a standby mode.

Shift-register circuit and shift-register unit

The present invention is related to a unit gain buffer of the driver circuit to drive the data line in the filed of LCD data driver, further to be preferably applied to the new TFT-LCD processing of low temperature poly-silicon. This invention is using the plurality of PMOS transistor connection to result in the almost same value between the Vout and Vin. There is no using of the feedback connection in this invention, so the using of the compensation capacitor can be avoided, furthermore the data driver layout area of the LCD driver can be reduced. This invention can improve the defect of the larger layout area result from the prior art.

Unit gain buffer

A scan driver of LCD with fault detection and correction circuit is disclosed herein. The scan driver fabricated on a glass substrate locates at both ends of the scan buses can simultaneously drive the scan buses from both ends. The fault detection and correction circuit of the scan driver is used to determine whether transmitting signal from a DFF at present stage into a DFF at next stage, or transmitting signal from the other DFF at present stage through a scan bus into the other DFF. The fault detection and correction circuit includes the first detecting device, the second detecting device, the control signal generating device, and the transmission control device. The first and the second detecting device generate a first logic level and a second logic level responding to a stuck-at-zero fault and a stuck-at-one fault respectively. The control signal generating device generates a first control signal when all input terminals exhibiting a second logic level, and generates a second control signal when one of input terminals exhibiting the first logic level. The transmission control device can transmit signal from one DFF to the other and to the scan bus responding to the first control signal, also can isolate them and the scan bus responding to the second control signal.

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Taipei, Taiwan

Bo-Wen Wang