Industrial Technology Research Institute

Phoenix Precision Technology Corporation

Unimicron Technology Corporation

Bo-Wei Chen

Shih-Ping Hsu

Hsien-Shou Wang

Szu-Kang Hsien

Yung-Hui Chung

Chia-Ming Tsai

Tim Kuei Shia

Chien-Hua Cheng

Tim-Kuei Shia

Bo-Jyun Kuo

Jia-Chun Huang

Ji-Eun Jang

A successive approximation register (SAR) analog-digital converter (ADC) and a method for operating the same are provided. The SAR ADC includes a first capacitor DAC (CDAC), a comparator and a controller. The first CDAC receives and samples an analog input signal to generate a first voltage. The comparator compares the first voltage with a comparison reference voltage to generate a first comparison result. In a k-th iteration of at least two iterations, the controller switches a k-th switching capacitor set from a first state to a second state, such that the first CDAC generates a second voltage, and the comparator compares the second voltage with the comparison reference voltage to generate a second comparison result. The controller determines a window region and determines whether the k-th switching capacitor set is switched back to the first state according to the first comparison result and the second comparison result.

Successive approximation register analog-to-digital converter and method for operating the same

A signal comparison apparatus and a method of controlling the same are provided. The signal comparison apparatus includes a first comparator, a self-timed clock generator and a controller. The first comparator is controlled by a start signal to compare differences of first input signals and generate output signals. The self-timed clock generator receives the output signals to generate a self-timed clock signal. The controller receives the self-timed clock signal and calculates a time interval of the self-timed clock signal which responds to the first input signals of the first comparator, and determines whether the time interval is equal to or larger than a threshold time to generate a metastable detection signal. When the time interval is equal to or larger than the threshold time, the controller outputs the metastable detection signal as the start signal, such that the first comparator continue comparing the next differences of the first input signals.

Signal comparison apparatus and method of controlling same

A latch apparatus and applications thereof are provided. The latch apparatus consists of a latch circuit and a switchable DC block unit. The switchable DC block unit is coupled to the latch circuit, and configured to: isolate a cross-coupling path in the latch circuit and store a voltage difference before the latch apparatus performs the latching operation; and when the latch apparatus performs the latching operation, provide the stored voltage varying with time to increase the overdrive voltage of at least one transistor in the latch circuit (increase the transistor transconductance), so that the latch apparatus maintains high speed operation at low supply voltage.

Latch apparatus and applications thereof

The present disclosure provides a dynamic comparator with equalization function including a preamplifier, switched latch and dynamic transconductance circuit. The preamplifier amplifies input signals of the dynamic comparator. The dynamic transconductance circuit is inserted between the preamplifier and the switched latch for operating in a reset mode or a comparison mode. When operating in the reset mode, the dynamic transconductance circuit in conjunction with the switched latch performs voltage equalization of output signals of the switched latch, or when operating in the comparison mode, the dynamic transconductance circuit in conjunction with the switched latch receives the output signals generated by the preamplifier and carries out signal transconductance. The switched latch generates output signals as a comparison result of the dynamic comparator based on the transconductance signals generated by the dynamic transconductance circuit. The present disclosure provides a dynamic comparator that reduces the power consumption and increasing the operating speed.

Dynamic comparator with equalization function

An analog-to-digital converting (ADC) apparatus is disclosed. The ADC apparatus includes a coarse comparing module, at least one pre-switching detection module, at least one fine comparing module, and an encoder. The coarse comparing module compares an input signal and a plurality of first reference signals to generate a previous comparing result and a coarse comparing result in sequence. The pre-switching detection module generates a plurality of previous selecting signals according to the received previous comparing result. The encoder generates a previous encoding result according to the coarse comparing result. The fine comparing module selects a selected reference signal to be compared with the input signal from a plurality of second reference signals according to the previous selecting signals and the previous encoding result, so as to generate a fine comparing result.

Analog to digital converting apparatus and method thereof

A comparison system including a dynamic comparator, a background offset calibration circuit, and an asynchronous reset timing control circuit is presented. The background offset calibration circuit is coupled to the dynamic comparator, and generates calibration signals in response to reference switching control signals. Where calibration signals are used to calibrate the input refer offset of the dynamic comparator. The asynchronous reset timing control circuit is coupled to the dynamic comparator and the background offset calibration circuit, and generates a control clock signal and the reference switching control signals in response to the output signals of the dynamic comparator and a plurality of basic clock signals. During each clock cycle of the first basic clock signal, the control clock signal is used to control the dynamic comparator to perform two data comparison, one for the input refer offset and the other for a differential input signal.

Dynamic comparator based comparison system

A dynamic comparator with background offset calibration is provided. The dynamic comparator includes at least one input differential pair, a first back-to-back inverter, a second back-to-back inverter, and an integrator. The input differential pair includes two current branches, wherein one of the current branches has an input referred offset. The first back-to-back inverter determines which one of the two current branches has the input referred offset in response to a first clock signal and generates two control signals accordingly. The integrator generates two calibration voltages for the input differential pair in response to the two control signals, so as to calibrate the input referred offset. The second back-to-back inverter determines a difference between two input signals received by the input differential pair after the input referred offset is calibrated in response to a second clock signal and outputs two comparison signals accordingly.

Dynamic comparator with background offset calibration

A novel analog-to-digital converter (ADC) architecture using subranging successive approximation approach is disclosed. The ADC architecture is capable of achieving high sampling rate, low power consumption and low complexity. It is also able to advance the chip production yield and area utilization ratio. The new proposed ADC is formed by combining a flash converter having high sampling rate and low resolution with a successive approximation converter having low power consumption and low sampling rate.

Analog-to-digital converting system

A switched-capacitor (SC) circuit relating to summing and integration algorithms is provided. The SC circuit submitted by the present invention benefits from better closed-loop bandwidth performance because of combining positive and negative feedback loops of a high gain amplifier. In addition, the SC circuit submitted by the present invention not only provides differential output signal obtained by a summing (or integration) algorithm of input voltage signals and reference voltage signals and forward drives such differential output signal to a next stage SC circuit, but also provides flexible and accurate coefficient design for every individual input and reference voltage signals in the said algorithm. Besides, if the circuit manner of alternate resetting is disabled or removed, the SC summing circuit submitted by the present invention can serve as an SC integration circuit.

Switched-capacitor circuit relating to summing and integration algorithms

The present invention relates to a method to fabricate a flip chip substrate structure, which comprises: providing a carrier; forming a patterned resist layer on the surface of the carrier; forming sequentially a first metal layer, an etching-stop layer, and a second metal layer; removing the resist layer, forming a patterned first solder mask, and then forming at least one first circuit build up structure thereon; forming additionally a patterned second solder mask on the circuit build up structure; respectively removing the carrier, the first metal layer, and the etching-stop layer; and forming solder bumps on both sides of the circuit build up structure. The method increases integration and achieves the purpose of miniaturization. The method solves the problem of circuit layer multiplicity and process complexity.

Method for fabricating a flip chip substrate structure

A bandgap reference circuit generating bandgap reference voltage/current. The bandgap reference circuit generates a negative temperature coefficient current (I) and the first and the second positive temperature coefficient currents (Iand I), and compensates the non-constant components of the current Iby multiplying the currents I, Iand Iby three specially designed numbers K, Kand K, respectively, and then summing up the results. The bandgap reference circuit transforms the summation current (K&#xb7;I+K&#xb7;I+K&#xb7;I) to generate a bandgap reference voltage or a bandgap reference current.

Bandgap reference circuit

A method of manufacturing a coreless package substrate together with a conductive structure of the substrate is disclosed. The method can produce a coreless package substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless package substrate with high density of circuit layout, less manufacturing steps, and small size.

Coreless package substrate with conductive structures

A method for manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.

Method to manufacture a coreless packaging substrate

A method of manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.

Growing community of inventors

Miaoli County, Taiwan

Bo-Wei Chen