Marvell International Limited

Qualcomm Incorporated

Marvellworld Trade Ltd.

Marvell Asia Pte., Ltd.

Bo Wang

Qiang Tang

Chih-Hsin Wang

Sang Won Son

Lydi Smaini

Neric Fong

Younghua Song

Runzi Chang

Yonghua Song

Hongyuan Zhang

Pantas Sutardja

Rohit U Nabar

Roberto Rimini

Nan Zhang

Atul Salhotra

Chuan-Cheng Cheng

Vijay Varadarajan

Ping Gao

Xinjie Yang

Chen Ma

A method for producing a semiconductor device, the method includes, forming, on a substrate made from a semiconductor substance, at least one bipolar junction (BJ) transistor including a first terminal connected to a first well, the first well formed in the substrate and includes a first dopant having a first dopant concentration. At least one non-BJ transistor is formed on the substrate, the non-BJ transistor includes a second terminal connected to a second well, and the second well formed in the substrate and includes a second dopant having a same polarity as the first dopant. The first dopant concentration of the BJ transistor is higher than the second dopant concentration of the non-BJ transistor.

Device having bipolar junction transistors and finFET transistors on the same substrate

Apparatus and methods are disclosed for determining, on a small form factor 5G communication device, the range of a target object include receiving, at a receiving antenna of the small form factor communication device, a composite signal where the composite signal includes a target reflection signal and a mutual coupling (MC) leakage signal, generating a composite beat waveform by mixing the composite signal with an original signal, where the composite beat includes target beat and MC leakage beat waveform components, isolating the target beat waveform by subtracting from the composite beat waveform a weighted, k-delayed composite beat waveform, where for a configured k the target beat waveforms are uncorrelated and the MC leakage beat waveforms are correlated, and determining, using the target beat waveform, a range of the target object from the small form factor device.

Mitigating mutual coupling leakage in small form factor devices

Aspects of the disclosure provide a circuit having an amplifier and a load current based control circuit. The amplifier is configured to detect a difference between a feedback voltage and a reference voltage, and control, based on the difference, a pass device to regulate an output voltage for supplying power to load devices. The feedback voltage is indicative of the regulated output voltage from the pass device. The load current based control circuit is configured to sense a load current output from the pass device to the load devices and generate a control signal to adjust a compensation capacitance based on the sensed load current to adjust a zero frequency of the circuit.

Adaptive opamp compensation

An apparatus including a resistor capacitor network that includes an integrated high resistance resistor on top of a MOS capacitor. The resistor capacitor network includes a metal oxide semiconductor capacitor portion that includes a high-k gate oxide layer. The value of k is in a range of 4.0 to 100.0. The resistor capacitor network further includes a high resistance polysilicon gate layer formed over the high-k gate oxide layer. The resistance of the polysilicon gate layer is in a range of 100 to 2000 ohms per square.

RC networks that include an integrated high resistance resistor on top of a MOS capacitor

The disclosure can provide methods and systems for autocalibrating a transceiver. The method can include upconverting a bandpass input signal by mixing the bandpass input signal with a first local oscillator signal to form an initial transmitter signal. The initial transmitter signal can be looped back to a receiver and downconverted with a second local oscillator signal having a frequency that is different from the first local oscillator to form an intermediate frequency signal. At least one of a gain and a phase of the transmitter can be adjusted based on a transmitter image sideband of the intermediate frequency signal to generate a calibrated transmitter signal having minimized transmitter image sideband.

On-chip I-Q imbalance and LO leakage calibration for transceivers

A wireless network device comprising a physical layer (PHY) module and a media access control (MAC) module. The PHY module is configured to communicate with an 80 MHz channel. The 80 MHz channel includes a plurality of sub-bands including a first sub-band, a second sub-band, a third sub-band, and a fourth sub-band. One of the plurality of sub-bands corresponds to a primary channel. The PHY module is further configured to determine which of the plurality of sub-bands are receiving a data packet, and generate at least one clear channel assessment signal indicating which of the plurality of sub-bands are receiving the data packet. The MAC module is configured to receive the at least one clear channel assessment signal from the PHY module, and selectively transmit on the primary channel based on the at least one clear channel assessment signal.

Coexistence mechanism for 802.11AC compliant 80 MHz WLAN receivers

A transmitter beamforming technique for use in a MIMO wireless communication system determines (i) a partial description of a reverse channel without determining a full dimensional description of the reverse channel and (ii) a partial description of a forward channel without determining a full dimensional description of the forward channel. A correction matrix is developed from the partial description of the reverse channel and a partial description of the forward channel. The correction matrix is used to process signals to be transmitted via the forward channel, and a steering matrix is used to perform beamforming in the forward channel.

Calibration correction for implicit beamformer using an explicit beamforming technique in a wireless MIMO communication system

A system is provided and includes an array of cells, a first module, and a third module. The first module reads a state of a cell in the array to detect first bits stored in the cell. The third module, subsequent to the first module reading the state, performs a first operation on a first bit of the first bits and performs the first operation on a first of multiple signal inputs. The signal inputs indicate second bits of data to be stored in the cell. The third module performs a second operation on a second bit of the first bits and performs the second operation on a second one of the signal inputs. The first module, based on results of the first and second operations, performs a first erase operation or a first program operation on the cell to match the state of the cell to the second bits.

Multi-level memory cell read, program, and erase techniques

In one embodiment, an apparatus includes an amplifier configured to receive an asymmetric signal. A first resistance is coupled between an input node and an output node of the amplifier. A second resistance is coupled to the input node of the amplifier. A first switch is configured to be controlled during a first interval to couple the second resistance to a positive resistance to increase a gain of the amplifier to correct the asymmetric signal. The gain is a function of the first resistance and a combination of the second resistance and the positive resistance. A second switch is configured to be controlled during a second interval to couple the second resistance to a negative resistance to decrease the gain of the amplifier to correct the asymmetric signal. The gain is a function of the first resistance and a combination of the second resistance and the negative resistance.

Asymmetric correction circuit with negative resistance

On-chip IQ imbalance and LO leakage calibration for transceivers

A low leakage power management system is provided. An external voltage domain is selectively coupled to the internal voltage domain of an integrated circuit according to demand for the functions provided by the integrated circuit. An external voltage Vis connected to the internal supply voltage plane of the integrated circuit when the integrated circuit is active. The external supply voltage Vis disconnected from the integrated circuit chip during idle periods. A plurality of switch cells may be provided for connecting the external voltage Vto the integrated circuit. A multi-step sequence is provided for connecting the external supply voltage Vto the chip's internal supply voltage plane to prevent excessive current from flowing through any individual switch cell.

Low leakage power management

On-Chip IQ imbalance and LO leakage calibration for transceivers

A level shifter including a level shifter module configured to i) receive an input signal, wherein the input signal varies between a first level and a second level, ii) receive a first voltage supply signal and a second voltage supply signal, and iii) generate a latch control signal based on the input signal and one of the first voltage supply signal and the second voltage supply signal. The level shifter further includes a latch module configured to i) receive the latch control signal, ii) receive the second voltage supply signal and a third voltage supply signal, and iii) generate an output signal based on the latch control signal and one of the second voltage supply signal and the third voltage supply signal.

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Sunnyvale, CA, United States of America

Bo Wang