Samsung Electronics Co., Ltd.

Cheil Industries Inc.

Oki Semiconductor Co., Ltd.

Bo Un Yoon

Il Young Yoon

Jin Woo Bae

Jong Hyuk Park

Ki Hoon Jang

Byoung Ho Kwon

Bong Sik Choi

Hye Sung Park

Jong Won Lee

Kil Sung Lee

Seung Hoon Choi

Shunichi Tokitoh

Jae Seok Lee

Hyo Jung Kim

Ki Chul Park

Chung Ki Min

Hyun Soo Roh

Chang Ki Hong

Hao Cui

Tae Min Earmme

Joon Sang Park

Chang Sun Hwang

Ja Eung Koo

Hee Sook Cheon

Sang Rok Hah

Ye Hwan Kim

Youn Cheol Jeong

Won Joong Do

No Ui Kim

Dong Hoon Kwon

Seiichi Kondou

Hyun Kyo Seo

Yang Hee Lee

Young Beom Pyon

Se Yun Park

Su Young Shin

Young Ho Koh

A method for fabricating a semiconductor device includes providing a polishing pad which includes a first region and a second region separated from each other by a fence, loading a wafer onto the first region, providing a slurry solution onto the first region, providing an ultrapure water onto the second region, turning the polishing pad to polish a surface of the wafer, and unloading the wafer from the polishing pad after polishing on the surface of the wafer is completed, wherein the fence includes a first fence extending from a center of the polishing pad toward an edge of the polishing pad in a first horizontal direction, and a second fence extending from the center of the polishing pad toward the edge of the polishing pad in a second horizontal direction different from the first horizontal direction.

Apparatus for polishing a wafer and method for fabricating a semiconductor device using the same

Substrate cleaning equipment includes a substrate holder which supports a substrate, a swing body, a head, a first cleaning liquid supply structure, and a second cleaning liquid supply structure. The swing body moves along a sweep line on a main surface of the substrate. The head is coupled to the swing body and includes a pad attachment surface facing the substrate holder. The first cleaning liquid supply structure is coupled to the swing body and sprays a first cleaning liquid onto the main surface of the substrate. The second cleaning liquid supply structure sprays a second cleaning liquid onto the main surface of the substrate. A buffing pad is attached to the pad attachment surface.

Substrate cleaning equipment, substrate treatment system including the same, and method of fabricating semiconductor device using the substrate cleaning equipment

A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.

Methods of manufacturing semiconductor devices

A semiconductor device that includes a plurality of word lines disposed on a substrate in which p-type and n-type active regions are defined, and extends in a first direction. A plurality of bit lines is disposed on the plurality of word lines and extends in a second direction, perpendicular to the first direction. A plurality of memory cells is disposed between the plurality of word lines and the plurality of bit lines and each includes a data storage pattern. The plurality of memory cells includes a plurality of dummy memory cells and a plurality of main memory cells. An upper surface of the data storage pattern of the main memory cells is higher than an upper surface of the data storage pattern of the dummy memory cells.

Semiconductor device having plural dummy memory cells

A method of forming a semiconductor device includes forming a mold structure on a substrate, forming a first mask layer having a deposition thickness on the mold structure and patterning the first mask layer to form first mask openings which expose the mold structure. The mold structure is etched to form holes that penetrate the mold structure. The first mask layer is thinned to form mask portions having thickness smaller than the deposition thickness. Conductive patterns are formed to fill the holes and the first mask openings. The first mask layer including the mask portions is etched to expose the mold structure. The conductive patterns include protrusions. A chemical mechanical polishing process is performed to remove the protrusions of the conductive patterns.

Method of forming semiconductor device

A method of manufacturing a semiconductor device includes preparing an object layer on a substrate; polishing the object layer with a first slurry including a first abrasive having a zeta potential of a first polarity; rinsing a surface of the object layer, using a rinsing solution including a chemical of a second polarity, opposite to the first polarity; and polishing the object layer with a second slurry including a second abrasive having a zeta potential of a second polarity, opposite to the first polarity.

Method of manufacturing a semiconductor device

A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.

Semiconductor devices including insulating capping structures

A semiconductor device with a damascene wiring structure which can prevent short-circuits between a seal ring and a wiring line or electrode pad. An upper layer barrier layer made from a conductive barrier material film is formed on an interlayer insulating film groove sidewall of the semiconductor device. Embedded in the groove is an upper layer seal ring wiring line with thickness of approximately 10 micrometers for instance, in which a plurality of isolated pockets of insulators are disbursed. These isolated pockets of insulators are formed using the interlayer insulating film which forms the damascene wiring line. Additionally, a first upper layer groove wiring line and a second upper layer groove wiring line are formed in an element forming region, and an upper layer barrier layer is formed on the outside perimeter. The upper layer seal ring wiring line and both upper layer wiring lines all have damascene wiring structures.

Semiconductor device having isolated pockets of insulation in conductive seal ring

Disclosed herein are slurry compositions for use in CMP(chemical mechanical polishing) process of metal wiring in manufacturing semiconductor devices, comprising a peroxide, an inorganic acid, a propylenediaminetetraacetate(PDTA)-metal complex, a carboxylic acid, a metal oxide powder, and de-ionized water, wherein the PDTA-metal complex plays a major role in improving overall polishing performance and reproducibility thereof by preventing abraded tungsten oxide from readhesion onto the polished surface, as well as in improving the dispersion stability of the slurry composition.

Slurry composition for use in chemical mechanical polishing of metal wiring

Growing community of inventors

Seoul, South Korea

Bo Un Yoon