Samsung Electronics Co., Ltd.

K. C. Tech Co., Ltd.

Bo-un Yoon

Sang-Jine Park

Chang-ki Hong

Jeong-Nam Han

Byoung-ho Kwon

Ho-young Kim

Kee-Sang Kwon

Sang-rok Hah

Jae-Jik Baek

Ji-Hoon Cha

Jong-Won Lee

Do-hyoung Kim

Kyoung-hwan Yeo

Kun-Tack Lee

Jae-Dong Lee

Keun-Hee Bai

Jae-Kwang Choi

Doo-Sung Yun

Myung-geun Song

Hyo-San Lee

Yong-Ho Jeon

Kwang-Yong Yang

Jong-won Lee

Ha-Young Jeon

Jung-Yup Kim

Young-rae Park

Bo-Kyeong Kang

Se-jung Park

Young-sang Youn

Seung-Jae Lee

Cheol Kyu Kim

Suk-Hun Choi

Jong-Heun Lim

Dae-Hyuk Kang

Il-Young Yoon

Seong-Kyu Yun

Jae-dong Lee

Won-Sang Choi

Ji-Won Yun

Si-Young Choi

Myeong-Cheol Kim

Young-Hoo Kim

Joon-Sang Park

Jae-seok Kim

Yong-Joon Choi

Byung-Kwon Cho

Ja-Eung Koo

Hee-Don Jeong

Geum-jung Seong

Ki-Hyung Ko

Ji-Min Jeong

In-Kwon Jeong

Sang-yeob Han

Ji-Eun Han

Suk-Hoon Jeong

Hong-kyu Hwang

Jin-wook Lee

Sang-Jin Kim

Sung-Jun Kim

Kyung-Hyun Kim

Jung-Min Oh

Woo-Gwan Shim

In-seak Hwang

Hong-soo Kim

Kwang-bok Kim

Jae-Phil Boo

Im-Soo Park

Won-Seong Lee

Chang-Sun Hwang

Sang-youn Jo

Yeon-Jin Gil

Sang-Hyun Park

Sang-Jin Hyun

Sang-Bom Kang

Dong-Chan Kim

Bon-Young Koo

Min-sang Kim

Jung-Won Lee

Hoon-Joo Na

Yoon-Hae Kim

Sang-kyun Kim

Kun-tack Lee

Dae-lok Bae

Kwang-Wook Lee

Young-kuk Kim

Jeong-sic Jeon

Hyung-seok Hong

Ju-hyun Kim

Hag-ju Cho

Jae-hee Kim

Kenji Takai

Dae-Young Kwak

Do-Yoon Kim

Jae-young Park

Kyu-hwan Chang

Yoo-Jung Lee

Jong-Su Kim

So-Ra Han

Seong-Ho Moon

Jung-Chan Lee

Disclosed is a slurry composition for chemical mechanical polishing (CMP) includes, as polishing particles, a complex compound of both fullerenol and alkylammonium hydroxide. The slurry composition, which exhibits excellent polishing properties, may be prepared at low cost in large quantities. Also disclosed is a method of preparing the slurry composition comprising obtaining a mixture of a fullerenol complex compound and unreacted hydrogen peroxide by reacting alkylammonium hydroxide, hydrogen peroxide, and fullerene, removing the unreacted hydrogen peroxide by adding hydrogen peroxide decomposition catalyst particles to the mixture, separating the hydrogen peroxide decomposition catalyst particles from the mixture by filtration, and adding a polishing additive to the mixture. Further disclosed is a method of fabricating a semiconductor device that includes providing a pattern defining a trench, forming a metal material film on the pattern to fill the trench, and performing CMP of the metal material film using the slurry composition.

Slurry composition for chemical mechanical polishing, method of preparing the same, and method of fabricating semiconductor device by using the same

A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

Semiconductor device and method for fabricating the same

Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

Semiconductor devices including a dummy gate structure on a fin

A slurry composition for chemical mechanical polishing, the slurry composition including ceramic polishing particles; a dispersion agent; a pH control agent and an additive having affinity with silicon nitride.

Slurry composition for chemical mechanical polishing

A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.

Methods of fabricating semiconductor devices including fin-shaped active regions

A chemical supplier includes a chemical reservoir containing a chemical mixture at a room temperature, an inner space of the chemical reservoir being separated from surroundings, a supply line through which the chemical mixture is supplied to a process chamber from the chemical reservoir, an inline heater positioned on the supply line and heating the chemical mixture in the supply line to a process temperature, and a power source driving the chemical mixture to move the chemical mixture toward the process chamber.

Chemical supplier, processing apparatus including the chemical supplier

A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.

Methods of forming semiconductor devices including trench walls having multiple slopes

Semiconductor devices are provided. A semiconductor device includes a fin protruding from a substrate. Moreover, the semiconductor device includes first and second gate structures on the fin, and an isolation region between the first and second gate structures. The isolation region includes first and second portions having different respective widths. Related methods of forming semiconductor devices are also provided.

Semiconductor devices including an isolation layer on a fin and methods of forming semiconductor devices including an isolation layer on a fin

A semiconductor device including a direct contact and a bit line in a cell array region and a gate electrode structure in a peripheral circuit region, and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate including a cell array region including a first active region and a peripheral circuit region including a second active region, a first insulating layer on the substrate, the first insulating layer including contact holes exposing the first active region, a direct contact in the contact holes, wherein a direct contact is connected to the first active region, a bit line connected to the direct contact in the cell array region and extending in a first direction, and a gate insulating layer and a gate electrode structure, wherein a dummy conductive layer including substantially the same material as the direct contact is in the peripheral circuit region.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first fin-type pattern on a substrate, having a first sidewall and a second sidewall opposed to each other; a first trench formed in contact with the first sidewall; a second trench formed in contact with the second sidewall; a first field insulating layer partially filling the first trench; and a second field insulating layer partially filling the second trench and a second field insulating layer partially filling the second trench. The second field insulating layer includes a first region and a second region disposed in a sequential order starting from the second sidewall, an upper surface of the second region being higher than an upper surface of the first field insulating layer. The device further includes a gate electrode on the first fin-type pattern, the first field insulating layer and the second field insulating layer, the gate electrode intersecting the first fin-type pattern and overlapping the second region.

A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

Methods for fabricating semiconductor device

Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.

Method of manufacturing semiconductor devices

Growing community of inventors

Seoul, South Korea

Bo-un Yoon