Taiwan Semiconductor Manufacturing Comp. Ltd.

Chunghwa Picture Tubes, Ltd.

Bo-Ting Chen

Wun-Jie Lin

Wan-Yen Lin

Jen-Chou Tseng

Kuo-Ji Chen

Yu-Ti Su

Sun-Jay Chang

Ming-Hsiang Song

Li-Wei Chu

Min-Chang Liang

Chia-Wei Hsu

Tsung-Hsin Yu

Nick Pai

Han-Jen Yang

Yuan-Ju Chan

Li-Chun Tien

Huan-Neng Chen

Jam-Wem Lee

Ting Yu Chen

Shao-Yu Li

Wei Yu Ma

Chang-Fen Hu

Yen-Lin Liu

Yang-Chi Yen

Jo-Yu Wu

Tzu-Heng Chang

Chia-Jung Chang

Ya-Hsiang Tai

Chia-Hui Chen

Huang-Chung Cheng

Guang-Cheng Wang

Chun-Hsiang Fang

A circuit device includes core circuitry. The circuit device further includes a first plurality of guard rings having a first dopant type, wherein the first plurality of guard rings is around a periphery of the core circuitry. The circuit device further includes a second plurality of guard rings having a second dopant type, wherein the second dopant type is opposite to the first dopant type, and at least one guard ring of the second plurality of guard rings is around a periphery of at least one guard ring of the first plurality of guard rings.

Guard ring and circuit device

Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.

Glitch preventing input/output circuits

Systems and methods are provided for a multiple power supply mode input/output (IO) circuit of an integrated circuit that includes a plurality of power rails, one or more supply mode power rails being associated with each supply mode of the integrated circuit, and a core power rail being associated with core circuitry of the integrated circuit. The IO circuit may further include a plurality of chip connection points, each chip connection point being connected to one or more of the power rails, the chip connection points being configured for connection to one or more package connection points.

Systems and methods for providing multiple GPIO supply modes

A method of protecting a device (protected device) (in a semiconductor system from an electrostatic discharge (ESD)) includes: coupling the protected device between a first node and a first reference voltage; coupling an ESD device between the first node and the first reference voltage; and selectively and actively coupling an input of the ESD device to a second reference voltage thereby selectively and actively turning on the ESD device.

ESD protection circuit, semiconductor system including same, and method for operating same

An electro-static discharge (ESD) protection network for an input/output (I/O) pad includes a driver stack including an upper branch and a lower branch, the upper branch being electrically connected between a first node that has a first reference voltage and the I/O pad, and the lower branch being electrically connected between the I/O pad and a second node that has a second reference voltage; a first ESD device electrically connected between the I/O pad and a third node that has a third reference voltage; and a power clamp between the third node and the second node.

Semiconductor device with ESD protection and methods of operating and configuring the same

A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Low dropout regulator circuits, input/output device, and methods for operating a low dropout regulator

An integrated circuit (IC) device includes a semiconductor substrate, a first connection tower, and one or more first front side conductors and one or more first front side metal vias. The semiconductor substrate includes a first semiconductor substrate segment having first functional circuitry and a second semiconductor substrate segment having a first electrostatic discharge (ESD) clamp circuit. The first connection tower connects to an input/output pad. The one or more first front side conductors and one or more first front side metal vias connect the first buried connection tower to the first functional circuitry in the first semiconductor substrate segment and to the first ESD clamp circuit in the second semiconductor substrate segment.

Integrated circuit and method of manufacturing same

A method of fabricating a semiconductor device includes forming a semiconductor substrate having a first protected circuit, and forming a first guard ring around the first protected circuit including: forming a first wall configured to provide a first reference voltage; and forming a second wall configured to provide a second reference voltage different than the first reference voltage.

Semiconductor device and method of manufacturing same

A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, an inverter, and a resistor-capacitor (RC) circuit coupled in series with the inverter between the input terminal and the output terminal. The RC circuit includes an NMOS transistor coupled between an RC circuit output terminal and a reference node, a resistor coupled between the RC circuit output terminal and a power supply node, and a capacitor coupled between the RC circuit output terminal and one of the power supply node or the reference node, and the inverter and the RC circuit are configured to generate an output signal at the output terminal based on the input signal.

Logic buffer circuit and method

A method of protecting a device (protected device) in a semiconductor system from an electrostatic discharge (ESD), the protected device being coupled between a first node and a first reference voltage, the method including: coupling an ESD device between the first node and the first reference voltage; coupling a shunting device between an input of the protected device and the first reference voltage; coupling a feedback control circuit between the first node and an input of the shunting device; and using the shunting device to actively couple the input of the protected device to the first reference voltage.

A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vddand an output, and a driven device having an input and a second supply voltage Vdd. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vddand the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.

ESD protection circuit cell

A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, a buffer, and an RC circuit coupled in series with the buffer between the input terminal and the output terminal. The RC circuit includes a first transistor and an RC network including a resistor and a capacitor, the first transistor is coupled in series with the resistor between a power supply node and a reference node, and the buffer and the RC circuit are configured to generate an output signal based on the input signal.

A method includes implanting a first guard ring around a periphery of core circuitry. The implanting of the first guard ring includes implanting a first component a first distance from the core circuitry on a first side of the core circuitry, and implanting a second component a second distance from the core circuitry on a second side of the core circuitry, wherein the second distance is greater than the first distance. The method further includes implanting a second guard ring around the periphery of the core circuitry. The implanting of the second guard ring includes implanting a third component a third distance from the core circuitry on the first side of the core circuitry, and implanting a fourth component a fourth distance from the core circuitry on the second side of the core circuitry, wherein the third distance is greater than the fourth distance.

Growing community of inventors

Fengyuan, Taiwan

Bo-Ting Chen