Samsung Electronics Co., Ltd.

Bo-Tak Lim

Gong-Heum Han

Soon-Moon Jung

Hoon Lim

Han-Byung Park

Hyou-Youn Nam

Byung-Gil Choi

Su-Yeon Kim

Choong-Keun Kwak

Chang-soo Lee

Jong-Pil Son

Hyuk-Joon Kwon

Jong-Soo Seo

Young-Kug Moon

Seung-Seob Lee

A semiconductor device includes a semiconductor die, a semiconductor integrated circuit and a three-dimensional crack detection structure. The semiconductor die includes a central region and a peripheral region surrounding the central region. The semiconductor integrated circuit is formed in the central region. The three-dimensional crack detection structure is formed in a ring shape in the peripheral region to surround the central region. The three-dimensional crack detection structure is expanded in a vertical direction. Using the three-dimensional crack detection structure, the crack penetration of various types may be detected thoroughly.

Semiconductor device including three-dimensional crack detection structure

A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

Semiconductor memory device having three dimensional structure

A semiconductor memory device comprises a cell region including a plurality of unit memory cells, and a peripheral circuit region, the peripheral circuit region including a plurality of peripheral circuit devices for operating the plurality of memory cells and at least one operating capacitor formed adjacent to at least one peripheral circuit device at a pseudo circuit pattern region.

Semiconductor memory device having a peripheral region including operating capacitors

Semiconductor device having three dimensional structure

A phase-change random access memory device is provided. The phase-change random access memory device includes a plurality of memory blocks, a main word line, a plurality of local word lines and a plurality of section word line drivers connected between the main word line and each of the plurality of local word lines and adapted to adjusting voltage levels of the plurality of local word lines in response of voltages applied to the main word line and block information. The plurality of section word line drivers include at least one first section word line driver and at least one second section word line driver. The first section word line drivers include pull-down devices while not including pull-up devices.

Phase-change random access memory device

A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.

Phase change memory device and memory cell array thereof

Semiconductor memory device and method for arranging and manufacturing the same

In a mode entrance control circuit and a mode entering method to stably enter a semiconductor memory device into a predetermined operating mode only when insensitive to a change of a process, temperature, or voltage, etc., and simultaneously satisfying a constant entrance condition, the mode entrance control circuit includes an operation control part for generating an operation enable signal when a first voltage applied through a first pad is over a first determination voltage, a voltage division part for dividing a second voltage applied through a second pad to generate a trimming reference voltage, and a mode entrance signal generating part operated in response to the operation enable signal, for comparing a level of an applied fixed reference voltage with a level of the trimming reference voltage, and for generating a mode entrance enable signal to allow the semiconductor memory device to enter into a predetermined mode.

Mode entrance control circuit and mode entering method in semiconductor memory device

Growing community of inventors

Gyeonggi-do, South Korea

Bo-Tak Lim