Cypress Semiconductor Corporation

Bo Soon Chang

Vani Verma

Carlo Gamboa

Dagmar Beyerlein

Thurman John Rodgers

Brett Alan Spurlock

Anthony Odejar

Oleksandr Karpin

Oleksandr Hoshtanar

Igor Kravets

Timothy M Lacey

Khushrav S Chhor

Fritz W Beyerlein

Carlo Melendez

Annie Tan

A sensor package includes at least one die, a fingerprint sensor, a mold material, and a land grid array. The fingerprint sensor is electrically coupled to the at least one die. The mold material encapsulates the at least one die. The land grid array layer is electrically coupled to the at least one die. The land grid array layer, the fingerprint sensor, and the mold material each include a common footprint.

Fingerprint sensor packages

Described is a semiconductor package frame including a material comprising wire openings a die-mounting surface area with a die-mounting surface and identification markings included within the die-mounting surface. The identification markings uniquely identify the semiconductor package frame from among other semiconductor package frames comprising different identification markings.

Semiconductor packaging identifier

An embodiment of the present invention is directed to a semiconductor packaging frame allowing identification information to be stored in the paddle area of the individual frame. Forming identification information on the paddle allows unique tracking of the semiconductor frame package during and after manufacturing and for tracking down variances, defects, and other problems during the semiconductor packaging process. Further, the shapes formed from the identification information provide increased surface area for bonding of the molding compound and thus strengthen the bond between the die paddle and molding compound thereby improving the strength of the semiconductor package.

A leadframe and semiconductor device package with multiple semiconductor device die paddles for accepting multiple semiconductor devices is disclosed, wherein the leadframe increases semiconductor device density and reduces cost by integrating the multiple dies into a semiconductor device package with a relatively small footprint. The leadframe may include at least one full-metal die paddle and at least one reduced-metal die paddle, which may form a unified or hybrid die paddle. The leadframe may enable electrical coupling of multiple semiconductor devices to a common leadfinger and/or die paddle, where internal leadfingers coupled to the common leadfingers and/or die paddles may receive the electrical coupling means from the semiconductor device. Surfaces of one or more die paddles of the leadframe may be exposed to the outside of the semiconductor device package to enable electrical testing of and/or provide heat dissipation from one or more of the semiconductor devices attached to the leadframe.

Multiple die paddle leadframe and semiconductor device package

In one embodiment, an integrated circuit package includes a lead frame with a die paddle and several leads. Portions of the lead frame not having an external electrical connection may be thinned such that they may be encapsulated by an electrically insulating packaging material on the back of the lead frame. Portions of the lead frame having external electrical connections may have a thickness such that they are exposed through the packaging material. The lead frame may be covered by an electrically insulating cover to protect components on the lead frame from erroneous electrical contact or electro-static discharge (ESD) damage.

Integrated circuit package with electrically isolated leads

A method and packaging for semiconductor devices and integrated circuits is disclosed that eliminates warpage stress on packages caused by coefficient of thermal expansion (CTE) mismatch between the device, lead frame or die paddle and a molding compound. Generally, the method includes steps of: (i) mounting the die on which the device is fabricated to a die paddle of a leadframe; and (ii) encapsulating the die on the die paddle and at least a portion of the leadframe in a molding compound, wherein a difference between a first volume of molding compound above a plane of the leadframe and a second volume of molding compound below the plane of the leadframe is sufficiently reduced to substantially eliminate warpage of the finished package due to mismatch of CTEs of the device, lead frame and packaging compound. The die paddle may be etched or reduced to facilitate molding compound flowing under the plane of the leadframe. Other embodiments are also disclosed.

Warpage-compensating die paddle design for high thermal-mismatched package construction

A semiconductor device package, a method of fabricating a semiconductor device package and a method of testing an integrated circuit utilizing a semiconductor device package are disclosed. Embodiments create a flip-flop semiconductor device package by coupling multiple leadfingers to conductive pads of a semiconductor device using an interposer with electrically conductive traces. The semiconductor device may be positioned in a face-up orientation between the leadfingers such that a single surface of the interposer may couple to both the semiconductor device and the leadfingers. The flip-flop package offers improved signaling properties, durability, reliability, and package density at reduced cost given that the interposer is configurable, the traces offer more reliable and durable interconnections, the interposer enables use of a smaller semiconductor device with a higher density conductive pad arrangement to decrease package density, and the interposer is relatively inexpensive.

Flip-flop semiconductor device packaging using an interposer

A semiconductor device package, a method of fabricating a semiconductor device package and a method of testing an integrated circuit utilizing a semiconductor device package are disclosed. Embodiments create a flip-flop semiconductor device package by coupling a semiconductor device, with a wire-bonded arrangement of conductive pads, in a face-up orientation beneath etched portions of multiple leadfingers. The flip-flop package offers improved signaling properties, durability, reliability, and package density at reduced cost given that the conductive pads of the device couple directly to the leadfingers, without requiring the manufacture of a new device or the rerouting of signal paths. The height of the package is also reduced by utilizing space beneath the etched portions of the leadfingers that was unused in conventional solutions. Additionally, the flip-flop configuration provides convenient means for exposing surfaces of the device and/or surfaces of the leadfingers.

Semiconductor device packaging using etched leadfingers

A method and system for controlling the processing of an IC chip assembly line using a central computer system and a common communication protocol. In one embodiment, a manufacturing execution system (MES) is used as the computer system and the communications protocol is the standard semi equipment communications standard/generic equipment model (SECS/GEM). One or more equipment cell controllers (CC) may be used to communicate between the MES a plurality of in-line substations which comprise the assembly line. Automated vision camera systems may also communicate information to the MES via the CCs. In one embodiment, the MES maintains a database in memory comprising processing history of a die-strip and results of automated die-strip examination from the vision camera systems. In one embodiment, the die-strip may be of a ball grid array (BGA) type.

System for controlling the processing of an integrated circuit chip assembly line

An integrated back-end integrated circuit (IC) manufacturing assembly is disclosed. In one embodiment, the present invention has a front-of-line portion comprising a plurality of integrated sub-stations for operating on a first plurality of die-strips on an in-line basis to produce a second plurality of die-strips. The present embodiment further comprises an end-of-line portion coupled to the front-of-line portion and comprising a plurality of integrated sub-stations for operating on the second plurality of die-strips on an in-line basis to produce die-strip components. The present embodiment also comprises an in-line test portion coupled to the end-of-line portion for testing the die-strip components. The present embodiment further comprises a finish portion coupled to the in-line test portion and comprising a plurality of integrated sub-stations operating on tested die-strip components. In addition, camera systems perform automated visual inspection of dies on the die-strip and maintain a database that can be used for automated reject management.

Integrated back-end integrated circuit manufacturing assembly

In one embodiment, an integrated circuit package includes a lead frame with a die paddle and several leads. Portions of the lead frame not having an external electrical connection may be thinned such that they may be encapsulated by an electrically insulating packaging material on the back of the lead frame. Portions of the lead frame having external electrical connections may have a thickness such that they are exposed through the packaging material. The lead frame may be covered by an electrically insulating cover to protect components on the lead frame from erroneous electrical contact or electrostatic discharge (ESD) damage.

An integrated circuit packaging device includes a laminate substrate. A first surface of the substrate can be mounted on an integrated circuit and the second surface can be mounted on a surface of a printed circuit board. The device can also include an array of lead contact pads on the first surface that can provide wire bond connections to circuit contact pads in the integrated circuit, and an array of solder ball contact pads on the second surface. Routing layers can provide electrical coupling between the lead contact pads on the first surface and the solder ball contact pads on the second surface. A dedicated contact pad on the first surface is electrically coupled to the laminate substrate.

Non-stick detection method and mechanism for array molded laminate packages

A method and system for universal packaging in conjunction with an automated in-line back-end IC manufacturing process. In one method embodiment, the present invention processes a die-strip through a number of integrated in-line processes that function independently of the die size of the die-strip. A control computer maintains a die-strip map database recording the die size of the die-strip. In-line molding and solder ball attachment processes are then performed and function independently of the die size of the die-strip. Processes that are independent of die size provide a universal packaging manufacturing solution. The present invention then accesses the database to determine the die size for cutting the die-strip based on specifications maintained by the electronic die-strip map database. Sorting, testing and finish assembly processes are then performed.

Method and system for universal packaging in conjunction with a back-end integrated circuit manufacturing process

A method of performing back-end manufacturing of an integrated circuit (IC) device is disclosed. In one method embodiment, the present invention processes a die-strip through a front-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The die-strip is then automatically provided to an end-of-line assembly portion. The die-strip is then processed through an end-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The present embodiment then automatically provides the die-strip to a test assembly portion. The die-strip is then tested by the test portion and then automatically provided to a finish assembly portion. The present embodiment then processes the die-strip through a finish portion which comprises a plurality of sub-stations operating on an in-line basis. Camera systems perform automated visual inspection of dies on the die-strip and maintain a database that can be used for automated reject management.

Method of performing back-end manufacturing of an integrated circuit device

A method and system for a reject management protocol within a back-end IC manufacturing process. In one method embodiment, the present invention implements a tracking process for a die-strip. The present invention also maintains an electronic die-strip map database, and utilizes the tracking process to update the electronic die-strip map database as the die-strip moves in an in-line fashion from one sub-station to another within the manufacturing process. Information used to update the database can originate from one or more automated visual camera systems used for quality assurance. In so doing, the present invention categorizes the die on the die-strip based on information maintained by the electronic die-strip map database. This information can be used for die sorting and for die rejection. In one embodiment, an identifying code is placed on each die strip that can automatically identify the die-strip using the automated camera systems.

Growing community of inventors

Cupertino, CA, United States of America

Bo Soon Chang