Skhynix Inc.

Bo Seok Jeong

Soon Young Kang

Dae Sung Kim

Wan Je Sung

Dong Sop Lee

Ie Ryung Park

Myung Jin Jo

A memory system includes: a memory block including a plurality of pages each comprising a plurality of memory cells connected to bit lines and a word line of word lines, an address manager configured to output addresses corresponding to the plurality of pages, and a system data manager configured to generate index data corresponding to the each of the addresses, the index data indicating whether user data is inverted, and output the index data and information on a memory cell in which the index data is to be stored, respectively. The system data manager is configured to, determine memory cells connected to different bit lines from among memory cells included in adjacent pages corresponding to consecutive addresses of the addresses, as memory cells in which index data corresponding to the consecutive addresses are to be stored.

Memory system having memory controller

A data processing device includes a plurality of variable nodes configured to receive and store a plurality of target bits; a plurality of check nodes each configured to receive stored target bits from one or more corresponding variable nodes of the plurality of variable nodes, check whether received target bits have an error bit, and transmit a check result to the corresponding variable nodes; and a group state value manager configured to determine group state values of variable node groups into which the plurality of variable nodes are grouped.

Data processing device

Provided herein may be an error correction decoder, an error correction circuit having the error correction decoder, and a method of operating the error correction decoder. The error correction decoder may include a calculator configured to output an error correction message by performing an iterative decoding operation on a first codeword, a syndrome generator configured to generate a syndrome by calculating the error correction message and a parity check matrix and to output a number of iterations representing the number of times the iterative decoding operation has been performed, and an unsatisfied check node (UCN) value representing the number of unsatisfied check nodes in the syndrome, and a speed selector configured to output a speed code for controlling a speed of the iterative decoding operation depending on the number of iterations and the UCN value.

Error correction decoder, error correction circuit having the same, and method of operating the same

Provided herein is an error correction decoder and a memory system having the same. The error correction decoder includes a memory configured to store a hard decision value of a variable node. The decoder further includes a flipping function value generator configured to generate, in an i-th iteration, a first value based on a number of unsatisfied check nodes (UCNs) corresponding to the variable node, and to generate a flipping function value as (i) a difference between the first value and an offset value or (ii) a set value, wherein i is a non-negative integer. The decoder also includes a comparator configured to output, in the i-th iteration, a first signal indicating whether to flip or not flip the hard decision value of the variable node in the memory based on comparing the flipping function value to a flipping threshold value.

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Incheon, South Korea

Bo Seok Jeong