Qualcomm Incorporated

Bo Pang

Ravindraraj Ramaraju

Animesh Datta

Xiaohong Quan

Rakesh Vattikonda

Andrew Weil

Qi Ye

De Lu

Samrat Sinharoy

Matthew Chauncey Kusbit

Benjamin Griffitts

Mahmoud Elhebeary

An apparatus, including: a switched capacitor configured to generate a switched capacitor voltage based on an input clock signal and a current; a current digital-to-analog converter (DAC) configured to generate the current based on a first digital signal; a first reference voltage generator configured to generate a first reference voltage; and a first voltage comparing device configured to generate a first frequency deviation detection signal based on a comparison of the switched capacitor voltage to the first reference voltage.

Clock frequency deviation detector with closed-loop calibration

In certain aspects, a circuit includes a dynamic differential logic gate having first and second outputs, and a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate. The dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal. The first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate.

Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors

A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR input is configured to receive a data input to the data-gated flip-flop. The data-gated flip-flop includes a first latch including a first latch data input and a first latch reset input, the first exclusive OR output being coupled to the first latch data input and the first latch reset input. The data-gated flip-flop includes a second latch having a data output, the data output coupled to the second exclusive OR input.

Low clock power data-gated flip-flop

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Carlsbad, CA, United States of America

Bo Pang