Sandisk Technologies Inc.

Splunk Inc.

Western Digital Technologies, Inc.

Bo Lei

Jun Wan

Huiwen Xu

Feng Q Pan

Zhenni Wan

Marios Iliofotou

Gerrit Jan Hemink

Mohsen Purahmad

Dana Lee

Jianmin Huang

George Apostolopoulos

Dongxiang Liao

Karthik Kannan

Jia Li

Chao-Han Cheng

Jeswanth Manikonda

Essam Zaky

Sitaram Venkatraman

Zhenming Zhou

Jiahui Yuan

Steven Theodore Sprouse

Guirong Liang

Anurag Singla

Ryan Lee Faircloth

Sathyanarayanan Kavacheri

Nidhi Agrawal

Peng Wang

Sadia R Poddar

Masaaki Higashitani

Deepanshu Dutta

Henry Chin

Yu-Chung Lien

Chris Avila

Gautam Ashok Dusija

Niles Yang

Xiying Costa

Tien-Chien Kuo

Anubhav Khandelwal

Jun Wang

Jonathan Huynh

Ravi J Kumar

Long C Pham

Yongke Sun

Abu Naser Zainuddin

Jonathan Hsu

Sung-En Wang

Xue Bai Pitner

Joanna Lai

Arash Hazeghi

Mahim Raj Gupta

Wenzhou Chen

Lanlan Gu

Shankar Guhados

Yihang Liu

Keyur Payak

Neil Darragh

Behrang Bagheri

The adaptive erase scheme includes erasing the memory cells of a selected memory block in at least one erase loop. During the at least one erase loop, simultaneously, an erase voltage is applied to a plurality of channels in the selected memory block, a first bias voltage is applied to the plurality of word lines of the first sub-block, and a second bias voltage is applied to the plurality of word lines of the second sub-block. The first bias voltage is different than the second bias voltage so that the memory cells of the first and second sub-blocks are erased at different speeds.

Adaptive erase scheme for a memory device

During a read operation for memory cells connected a selected word line, a memory system adjusts the overdrive voltage applied to word lines adjacent the selected word line in order to compensate for margin degradation between the erased data state and the lowest programmed data state.

Non-volatile memory with overdrive voltage zoning to compensate for reduced margins

A memory device includes a memory block comprising a plurality of memory cells and control circuitry configured to perform a read level acquisition operation to determine optimal read levels for reading a plurality of data states of the plurality of memory cells. To perform the read level acquisition operation, the control circuitry is configured to supply a read level acquisition waveform to the plurality of memory cells, obtain data miss compare (DMC) values for the plurality of memory cells based on the read level acquisition waveform, and identify the optimal read levels for the plurality of data states based on the DMC values. The control circuitry is further configured to perform a read operation on the plurality of memory cells in accordance with the optimal read levels as identified based on the DMC values.

Binary read-based fast algorithm for optimal read level acquisition

A non-volatile memory system detects an indication of erase depth of a population of memory cells and adjusts the programming process for the memory cells based on the detected erase depth.

Non-volatile memory with erase depth detection and adaptive adjustment to programming

A memory device includes control circuitry configured to perform an erase operation to erase memory cells of a memory block and perform an erase verify operation to verify whether the memory cells were sufficiently erased. To perform the erase operation, the control circuitry is configured to supply a first erase voltage pulse, perform the erase verify operation subsequent to supplying the first erase voltage pulse, subsequent to the erase verify operation, supply a first bias voltage to a first one of a plurality of memory strings and a second bias voltage different than the first bias voltage to a second one of a plurality of memory strings, and, while supplying the first and second bias voltages, supply a second erase voltage pulse. The second bias voltage is configured to inhibit the second erase voltage pulse supplied to the memory cells of the second one of the plurality of memory strings.

Adaptive single-side erase to improve cell reliability

An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: erase a block; verify, using a first erase verify level, that the block was properly erased; verify, using a second erase verify level, that the block was properly erased; determine whether there are any mismatches in a plurality of verify statuses between neighboring wordlines of the block from verifying the block using the second erase verify level; and identify, based on the determination, whether the block has failed.

Smart early detection of wordline-memory hole defects with wordline-dependent dual sensing during erase verify

The memory device includes a control circuitry that is communicatively coupled to memory cells are arranged in a plurality of word lines. The control circuitry is configured to perform a first programming pass on a selected word line. The first programming pass includes a plurality of programming loops, each of which includes the application of a programming pulse (Vpgm). The programming pulse voltage is increased between programming loops of the first programming pass by a step size. The step size is a first step size between two programming loops of the first programming pass and is a second step size that is different than the first step size between two other programming loops of the first programming pass. The control circuitry is also configured to perform a second programming pass to further program the memory cells of the selected word line to the plurality of data states.

Variable programming voltage step size control during programming of a memory device

The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells.

Techniques for reading memory cells in a memory device during a multi-pass programming operation

An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

Method to optimize first read versus second read margin by switching boost timing

A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data state of the first word line exceeds the critical voltage by a threshold. In response to the upper tail of the erased data state exceeding the critical voltage by the threshold, the controller then alternates between the first and second programming passes until the first programming pass is completed on the remaining word lines of the memory block.

Multi-pass programming operation sequence in a memory device

The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.

Verify techniques for current reduction in a memory device

A memory device that dynamically adjusts the sense time to read an open block of a memory block is disclosed. The adjusted sense time is based upon various considerations, including the sense time of the closed block equivalent and the openness of the open block. This allows the memory device to maintain a fixed Vt as well as reduce failed bit count, i.e., read errors due to an insufficient sense time. Also, the dynamic adjustment of sense time can optimize system performance and increase efficiency.

Systems and methods for dynamically sensing a memory block

A network connection between a server group of a data intake and query system and each of one or more source network nodes is established. Source data at the server group is received from at least one of the one or more source network nodes via the respective network connections and transformed, by the indexer server, to timestamped data entries of machine data. A model management server detects data constraints for a security model that include a data element used by the security model and an availability requirement set. Using the timestamped data entries, the data constraints are validated, and the validation used to determine a data availability assessment of the security model.

Systems data availability validation

Apparatus and methods for recovery after an abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.

Data storage systems and methods for improved recovery after a write abort event

Apparatuses and techniques are described for modifying program and erase parameters in a memory device in which memory cells can be operated in a single bit per cell (SLC) mode or a multiple bits per cell mode. In one approach, the stress on a set of memory cells in an SLC mode is reduced during programming and erasing when the number of program-erase cycles for the block in the SLC mode is below a threshold. For example, during programming, the program-verify voltage and program voltages can be reduced to provide a shallower than normal programming. During erasing, the erase-verify voltage can be increased while the erase voltages can be reduced to provide a shallower than normal erase. When the number of program-erase cycles for the block in the SLC mode is above the threshold, the program and erase parameters revert to a default levels.

Modifying program and erase parameters for single-bit memory cells to improve single-bit/multi-bit hybrid ratio

Growing community of inventors

San Ramon, CA, United States of America

Bo Lei