Phison Electronics Corporation

Bo-Jing Lin

Sheng-Wen Chen

Jen-Chu Wu

Yu-Chiang Liao

Shih-Yang Sun

Po-Min Cheng

Yen-Po Lin

A clock and data recovery circuit, a memory storage device and a signal adjustment method are disclosed. The method includes: detecting a phase difference between a first signal and a clock signal; generating a vote signal according to the phase difference and a first clock frequency; sequentially outputting a plurality of adjustment signals according to the vote signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the sequentially output adjustment signals.

Clock and data recovery circuit, memory storage device and signal adjustment method

A signal receiving circuit, a memory storage device and a signal receiving method are provided. The signal receiving circuit includes an equalizer module, a clock and data recovery (CDR) circuit and a controller. The equalizer module is configured to receive a first signal and compensate the first signal to generate a second signal. The CDR circuit is configured to perform a phase locking on the second signal. The controller is configured to open or close a signal pattern filter of the CDR circuit according to the second signal, wherein the signal pattern filter is configured to filter a signal having a specific pattern in the second signal.

Signal receiving circuit, memory storage device and signal receiving method

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Keelung, Taiwan

Bo-Jing Lin