Mediatek Singapore Pte. Ltd.

Changxin Memory Technologies, Inc.

Bo Hu

Kun Lan

Hao He

Guangteng Long

Dan Lu

Yiming Tang

The present disclosure provides a memory test method, a storage medium and a computer device. The memory test method comprises: obtaining a target test pattern that needs to be written into a plurality of chip interfaces, the plurality of chip interfaces being connected to a plurality of physical interfaces in a one-to-one correspondence; determining second information of the chip interfaces corresponding to first information of the physical interfaces, and using the first information and the second information as corresponding connection information; remapping the corresponding connection information to obtain mapped connection information; and determining, according to the target test pattern and the mapped connection information, an initial test pattern that needs to be written into the physical interfaces.

Memory test method, storage medium and computer device

An impedance matching circuit and an interface circuit are provided. The impedance matching circuit includes a reference-voltage generation circuit, a control-signal generation circuit, and a circuit subunit. The reference-voltage generation circuit generates a reference voltage. The control-signal generation circuit generates a plurality of control signals. The circuit subunit is coupled to the reference-voltage generation circuit and the control-signal generation circuit. The circuit subunit receives the reference voltage and the control signals. The circuit subunit includes a plurality of transistors. The plurality of transistors are turned on or off according to levels of the control signals, and the plurality of transistors provide an impedance which matches the impedance of a receiver when the interface circuit is powered. The reference voltage is provided to bulks of the transistors, so that the voltages of the bulks of the transistors are not equal to zero volts.

Impedance matching circuits and interface circuits

A current-mode logic circuit is provided. The current-mode logic circuit includes a transmitter module. The transmitter module includes an output impedance circuit, a switch circuit, and a current source. The output impedance circuit provides an adjustable output resistor. The adjustable output resistor includes floating resistors and/or pull-up resistors. The switch circuit is coupled to the output impedance circuit. The switch circuit receives differential input signals, outputs differential output signals, and controls high-low level switching of the differential input signals and the differential output signals according to the adjustable output resistor. The current source is coupled to the output impedance circuit and the switch circuit. The current source provides currents to the output impedance circuit and the switch circuit. The floating resistors are resistors coupled between the differential output signals, and the pull-up resistors are resistors coupled between the differential output signals and a power source.

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Hefei, China

Bo Hu