Fifth Electronics Research Institute of Ministry of Industry and Information Technology

China Electronic Product Reliability and Environmental Testing Research Institute

China Electronic Product Reliability and Environmental Testing Research Institute ((the Fifth Electronic Research Institute of Ministry of Industry Anbd Information Technology (ceprei))

Bo Hou

Yiqiang Chen

Yunfei En

Dengyun Lei

Wenxiao Fang

Yun Huang

Lichao Hao

Yudong Lu

Shuo Zhang

Changjian Zhou

Ang Li

Yihang Lin

Dazhi Wang

Yuan Liu

Haipin Wu

Haofan Long

In a method for monitoring a degradation mechanism of a switch device in a power conversion circuit. When individually determining the degradation mechanism of internal defects of the switch device, it is determined through a change trend of a real-time current change rate that internal defect degradation is caused by an increase of an oxide layer defect density or an interface defect density. It is confirmed through a decrease in the real-time current change rate that internal defect degradation is caused by the increase of the oxide layer defect density. When the real-time current change rate increases, it is determined through a secondary testing including the on-state resistance and low-frequency noise testing that degradation is caused by accurate packaging and/or the increase of the interface defect density.

Method for monitoring degradation mechanism of switch device in power conversion circuit

Disclosed are a method and device for detecting system failure, a computer device, and a storage medium. The method includes obtaining, when a system to be detected is powered on or off, a real-time voltage oscillation signal acquired by a voltage sensor arranged in a detection circuits of the system. The detection circuit is a circuit where a source and drain of a switching device in the system are located. A degradation trend of the system is determined according to the real-time voltage oscillation signal and a reference voltage oscillation signal corresponding to the detection circuit of the system. A failure detection for the system is performed according to the degradation trend of the system.

Method and device for detecting system failure, computer device, and storage medium

Disclosed are a method, device and system for health monitoring of SoC. The method includes: acquiring in real time sensor data of sensors monitoring SoC performance, the sensor data including reliability degradation sensor data, temperature sensor data, noise sensor data and current sensor data; extracting characteristic data representative of the SoC performance from the sensor data; performing analysis and prediction on the characteristic data in real time by using a prediction algorithm to obtain a performance state and a performance degradation trend of the SoC; outputting performance state information and performance degradation trend information of the SoC. The disclosed method, device and system for health monitoring of SoC can monitor the performance state of the SoC in real time and predict the performance degradation trend of the SoC in real time.

Method, device and system for health monitoring of system-on-chip

An ESD failure early warning circuit for an integrated circuit is disclosed, including a positive voltage stress generation module, a negative voltage stress generation module, a buck module, a warning output module, capacitors C, C, and diodes D, D, D, Dand D. The ESD failure early warning circuit can report a warning timely when there is an ESD event in the monitored integrated circuit, to improve the reliability of the device effectively. Moreover, the stress voltage generated by the positive voltage stress generation module and the negative voltage stress generation module is adjustable, so the stress voltage can be set flexibly by a user according to actual condition of the monitored integrated circuit. The present invention has high flexibility and wide application prospect.

ESD failure early warning circuit for integrated circuit

An on-chip TDDB degradation monitoring and failure early warning circuit for SoC. A control circuit module converts Qand Qsignals into a switch state control signal and outputs the switch state control signal to a digital conversion module for TDDB performance degradation. A MOS transistor of a first MOS transistor circuit within the digital conversion module for TDDB performance degradation is in a stress state of a supply voltage, and a MOS transistor of a second MOS transistor circuit is in a non-stress state. The first and second MOS transistor circuits output a first frequency value and a second frequency value to the output selection module. The output selection module outputs the first frequency value from the digital conversion module to the counter B for recording, or outputs the second frequency value to the counter A for recording. The counter module determines the degradation level of TDDB performance.

On-chip TDDB degradation monitoring and failure early warning circuit for SoC

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Guangzhou, China

Bo Hou