Samsung Electronics Co., Ltd.

Bo-Geun Kim

Yeong-taek Lee

Jae-Yong Jeong

Yong-Kyu Lee

Dae-seok Byeon

Hyun-Kook Park

Ki-Tae Park

Kye-Hyun Kyung

Chul-Ho Lee

Seok-cheon Kwon

Heung-Soo Lim

Jae-woo Im

Heung-soo Lim

Seung-Hun Choi

Hyun-Jun Yoon

Jae-Woo Lim

Jin-Yub Lee

Chi-Weon Yoon

Seung-Keun Lee

Yoon-Hee Choi

Jong-Hoon Lee

Dae-Yong Kim

Hyo-Jin Kwon

Sang-Yong Yoon

Myung-Hoon Choi

Jae-Woo Park

Jun-yong Park

Seung-Hwan Shin

Sung-Yeon Lee

Joon Young Kwak

You-Sang Lee

Myoung-Hoon Choi

Hwa-seok Lee

A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Memory system controlling peak current generation for a plurality of memories by synchronizing internal clock of each memory with a processor clock at different times to avoid peak current generation period overlapping

A memory device includes a memory cell array having multiple memory cells arranged respectively in regions where first signal lines cross second signal lines. The memory device further includes a decoder having multiple line selection switch units connected respectively to the of first signal lines. Each of the multiple line selection switch units applies a bias voltage to a first signal line corresponding to each of the multiple line selection switch units in response selectively to a first switching signal and a second switching signal, voltage levels of which are different from each other in activated states.

Resistive memory device and method of operating the same

Provided are a resistive memory device including a plurality of memory cells, and a method of operating the resistive memory device. The resistive memory device includes a sensing circuit connected to a first signal line, to which a memory cell is connected, the sensing circuit sensing data stored in the memory cell based on a first reference current; and a reference time generator for generating a reference time signal that determines a time point when a result of the sensing is to be output, based on the first reference current.

Resistive memory device and operating method

A resistive memory device includes a memory cell array including a plurality vertically stacked layers having one layer designated as an interference-free layer and another layer designated as an access prohibited layer, wherein the interference-free layer and the access prohibited layer share a connection with at least one signal line and access operations directed to memory cells the access prohibited layer are prohibited.

Resistive memory device, resistive memory system, and method of operating resistive memory device

A memory system includes a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Memory system controlling peak current generation for a plurality of memories by monitoring a peak signal to synchronize an internal clock of each memory by a processor clock at different times

A method is provided for driving a nonvolatile memory device. The method includes selecting first write drivers based on a predetermined current, performing a first program operation on resistive memory cells corresponding to the first write drivers, verifying whether the resistive memory cells have passed or failed in the first program operation and sorting information regarding failed bit memory cells that failed in the first program operation, selecting second write drivers based on the sorted failed bit memory cell information, and performing a second program operation on resistive memory cells corresponding to the second write drivers.

Nonvolatile memory device having variable resistive elements and method of driving the same

A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage.

Method of operating memory device

A memory device useable with a memory system includes a voltage generator to a plurality of first candidate voltages and a plurality of second candidate voltages, and an X decoder to sequentially apply each of the plurality of first candidate voltages and each of the plurality of second candidate voltages to one or more cells of a memory cell array, and then to apply one of the plurality of first candidate voltages and one of the plurality of second candidate voltages as a first read voltage and a second voltage, respectively, to read data from the cells of the memory cell array according to a characteristic of the cells of the memory cell array.

Apparatus and method of operating memory device

A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and a down write pulse signal when the data is second data type.

Nonvolatile resistive memory device and writing method

Driving methods of a nonvolatile memory device are provided. The driving method includes providing a start pulse adjusted based on a previous write operation to a resistive memory cell to write data, verifying whether the data has accurately been written using the start pulse, and executing a write operation on the resistive memory cell by an incremental one-way write method or a decremental one-way write method according to the verify result. Related nonvolatile memory devices are also provided.

Nonvolatile memory devices using variable resistive elements and related driving methods thereof

In an operating method for a nonvolatile memory device, first random data is sensed from a source area of the memory cell array, the first random data having been generated using first random sequence data. While sensing the first random data, third random sequence data is loaded to a page buffer circuit, the third random sequence data being generated from the first random sequence data and second random sequence data. A logical operation is performed on the sensed first random data and the third random sequence data in the page buffer circuit to generate second random data, and the second random data is programmed to a target area in the memory cell array different from the source area.

Method of operating nonvolatile memory devices storing randomized data generated by copyback operation

A method is provided for operating a memory system. The method includes reading nonvolatile memory cells using a first soft read voltage, a voltage level difference between the first soft read voltage and a first hard read voltage being indicated by a first voltage value; and reading the nonvolatile memory cells using a second soft read voltage paired with the first soft read voltage, a voltage level difference between the second soft read voltage and the first hard read voltage being indicated by a second voltage value. The second voltage value is different than the first voltage value. Also, a difference between the first voltage value and the second voltage value corresponds to the degree of asymmetry of adjacent threshold voltage distributions among multiple threshold voltage distributions set for the nonvolatile memory cells of the memory system.

Memory system and method of operating memory system using soft read voltages

A semiconductor memory device comprises a memory cell array configured to store data, a sensing unit configured to perform a read operation the memory cell array by sensing a bitline in a plurality of reading steps in response to a single read command, and a sensing time controller configured to generate a control signal to control a variable reading time for each reading step of the sensing unit.

Semiconductor memory device and related methods for performing read and verification operations

A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.

Flash memory device and method of testing the flash memory device

A reference voltage generating circuit provides a stabilized reference voltage and includes; a clock generator providing a clock signal, a high voltage generator providing a pumping voltage in response to the clock signal, a ripple eradicator providing a static voltage by removing voltage ripple from the pumping voltage, and a reference voltage generator providing the reference voltage.

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Suwon-si, South Korea

Bo-Geun Kim