Wenzhou University

Ningbo University

Zhejiang Rongpeng Air Tools Co., Ltd.

Bo Chen

Pengjun Wang

Gang Li

Yuejun Zhang

Yue Jun Zhang

Xiaorong Li

Fazheng Yang

Hao Ye

Xiangyu Li

Junpeng Wei

Zhen Li

Li Ni

Yunfei Yu

Di Zhou

Jiana Lian

Hongzhen Fang

Zhenxing Ying

Mingbo Wang

Xiaochun Guan

Liwei Li

Hai Ming Zhang

A signal processing circuit for a tunneling magnetoresistance sensor comprises thirty-eight MOS transistors, two capacitors and ten switches. A first switch, a second switch, a third switch, a fourth switch, a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor form a high-frequency modulation circuit. A fifth switch, a sixth switch, a seventh switch, an eighth switch, a seventeenth transistor, a twenty-second MOS transistor and a twenty-third MOS transistor form a high-frequency demodulation circuit. A signal output by a tunneling magnetoresistance sensor is modulated to a chopping frequency by the high-frequency modulation circuit, and is then demodulated by the high-frequency demodulation circuit.

Signal processing circuit for tunneling magnetoresistance sensor

A reliable multi-information entropy PUF for Internet of Things security includes a control circuit, a data register, 128 glitch generation circuits, a 128-to-1 multiplexer, and a Schmidt glitch sampling module. The control circuit controls the data register to generate a square signal, the 128 glitch generation circuits to generate glitch signals to be output and the 128-to-1 multiplexer to select the glitch signals to be output. The Schmidt glitch sampling module samples the glitch signals to obtain PUF response outputs. Each glitch generation circuit generates a glitch signal by means of a fully symmetrical structure. The Schmidt glitch sampling module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a buffer module and a D flip-flop.

Reliable multi-information entropy physical unclonable function (PUF) for internet of things security

An adaptive anti-aging sensor based on a cuckoo algorithm, comprising a control module, a reference voltage-controlled oscillator, two shaping circuits, a frequency difference circuit, a resolution adjustment circuit, a 16-bit counter, a parallel-to-serial circuit, an adaptive module, and a digital-to-analog converter. A lookup table is prestored in the adaptive module; when aging monitoring is performed on a voltage-controlled oscillator in an integrated circuit, the adaptive module uses the cuckoo algorithm to determines the optimal working voltage of the currently monitored voltage-controlled oscillator, and the control module accordingly changes the input voltage of the voltage-controlled oscillator of the integrated circuit. The present invention has the advantages that the degree of aging of the integrated circuit is reflected by monitoring the degree of aging of the voltage-controlled oscillator in the integrated circuit, and the optimal working voltage of the voltage-controlled oscillator in the integrated circuit is adaptively adjusted.

Adaptive anti-aging sensor based on cuckoo algorithm

A control flow attacks based on return address signatures comprises: using a return address as a push return address when a response is given to an interrupt service routine; generating an encrypted push return address by an XOR encryption circuit by means of an n-bit binary key generated by a pseudo random number generator; then, generating a push_address signature value by an MD algorithm signature circuit; when the response to the interrupt service routine is over, reading an n-bit binary address out of a stack to serve as a pop return address; generating an encrypted pop return address by the XOR encryption circuit; generating a pop address signature value by the MD algorithm signature circuit; comparing the push_address signature value with the pop address signature value; and determining whether or not a data processor is under a control flow attack according to a comparison result.

Detection method of control flow attacks based on return address signatures

A method for integrated optimization of a ternary FPRM circuit comprises: establishing an area estimation model, a power consumption estimation model and a delay estimation model of a ternary FPRM circuit under a p polarity; constructing a correlation between a multi-objective teaching-learning optimization algorithm and optimization of an area, power consumption and a delay of the ternary FPRM circuit; expressing positions of the individuals in the multi-objective teaching-learning optimization algorithm as polarities of the ternary FPRM circuit, and expressing a search space as a space for polarity selection of the ternary FPRM circuit; and finally, searching for a set of Pareto optimum polarity solution for the area, power consumption and delay of the ternary FPRM circuit by means of the multi-objective teaching-learning optimization algorithm to complete the optimization of the area, power consumption and delay for the ternary FPRM circuits.

Method for integrated optimization of ternary FPRM circuit

A true random number generator with a dynamic compensation capacity comprises a loop control logic, a shift register, a sensitive amplifier and a load matching unit. The sensitive amplifier comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor and two NMOS arrays. Each NMOS array comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor. The load matching unit comprises a first D flip-flop and a second D flip-flop and is connected at an output terminal and an inverted output terminal of the sensitive amplifier. The true random number generator has the advantages of simple feedback regulation and high robustness.

True random number generator with dynamic compensation capability

A true random number generator with stable node voltage comprises a loop control logic, two inverters identical in structure, two D flip-flops identical in structure, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a monitoring module and a post-processing module. Each inverter comprises a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor and an eleventh PMOS transistor. The true random number generator has the advantages of being able to eliminate the capacitive coupling effect and has high randomness.

True random number generator with stable node voltage

A carbon nanotube ternary SRAM cell with an improved stability and low standby power comprises a write bit line, a read bit line, a column select bit line, an inverted column select bit line, a write word line, an inverted write word line, a read word line, an inverted read word line, a first P-type CNFET, a second P-type CNFET, a third P-type CNFET, a fourth P-type CNFET, a fifth P-type CNFET, a sixth P-type CNFET, a seventh P-type CNFET, an eighth P-type CNFET, a ninth P-type CNFET, a first N-type CNFET, a second N-type CNFET, a third N-type CNFET, a fourth N-type CNFET, a fifth N-type CNFET, a sixth N-type CNFET, a seventh CNFET, an eighth N-type CNFET and a ninth N-type CNFET. The carbon nanotube ternary SRAM cell has the advantages of being lower in power consumption, capable of solving the half-select problem and the read-disturb problem and high in static noise margin.

Carbon nanotube ternary SRAM cell with improved stability and low standby power

A disposable cleaning-free paint pot comprise a pot body and a pot lid covering an opening of the pot body, the pot lid including a pot lid connector and a feed hole disposed in the pot lid connector, the adapter including an external thread disposed at an outer wall, positioning blocks disposed at an inner wall thereof, a press plate and a clamping cam; the pot lid joint is including positioning slots engaging with the positioning blocks and an annular groove for the clamping cam. The paint pot from cleaning after spray coating, the cleanliness of paint pot is guaranteed, so that the paint pot is fitted on spray gun rapidly, and the paint can be mixed in the pot body.

Disposable cleaning-free paint pot

A data selector based on TVD includes two AND gates, an OR gate, and three buffers, wherein the two AND gates and the OR gate adopt a three-phase dual-track pre-charge logic as a work logic. The data selector fulfills one time of evaluation operation and has three stages in one cycle. When a discharge control signal and a pre-charge control signal are at low levels, the data selector enters a pre-charge stage. When an evaluation signal is changed to a high level from a low level, the data selector implements the evaluation operation to fulfill the circuit function. When the discharge control signal is changed to a high level from the low level, the data selector enters a discharge state and gets ready for the next evaluation operation.

Growing community of inventors

Zhejiang, China

Bo Chen