Intel Corporation

Blas Cuesta

Qiong Cai

Serkan Ozdemir

Nevin Hyuseinova

Ferad Zyulkyarov

Marios Nicolaides

Dyer Rolan

A method to request memory from a far memory cache and implement, at an operating system (OS) level, a fully associative cache on the requested memory. The method includes pinning the working set of a program into the requested memory (pin buffer) so that it is not evicted due to cache conflicts and is served from the fast cache and not the slower next level memory. The requested memory extends the physical address space and is visible to and managed by the OS. The OS has the ability to make the requested memory visible to the user programs. The OS has the ability to manage the requested memory from the far memory cache as both a fully associative cache and a set associative cache.

Method for pinning data in large cache in multi-level memory system

Techniques and mechanism to provide a cache of cache tags in determining an access to cached data. In an embodiment, a tag storage stores a first set including tags associated with respective data locations of a cache memory. A cache of cache tags store a subset of tags stored by the tag storage. In response to any determination that a tag of the first set is to be stored to the cache of cache tags, all tags of the first set are stored to the first portion. Any storage of tags of the first set to the cache of cache tags includes storage of the tags of the first set to only a first portion of the cache of cache tags. In another embodiment, a replacement table is maintained for use in determining, based on an indicated level of activity for a set of the cache of cache tags, whether the set is to be selected for eviction and replacement of cached tags.

Method, apparatus and system to cache sets of tags of an off-die cache memory

Embodiments of methods, apparatuses, and storage media for memory imbalance prediction-based cache memory management are disclosed herein. In one instance, the apparatus may include a memory controller associated with a memory having a plurality of storage units. The memory controller may include logic configured to determine whether the memory enters into an imbalance state based at least in part on a difference in numbers of pending access requests to different storage units, and cause an adjustment of replacement management of a cache memory, based at least in part on a result of the determination. Other embodiments may be described and/or claimed.

Memory imbalance prediction based cache management

Techniques and mechanisms for adaptively changing between replacement policies for selecting lines of a cache for eviction. In an embodiment, evaluation logic determines a value of a performance metric which is for writes to a non-volatile memory. Based on the determined value of the performance metric, a parameter value of a replacement policy is determined. In another embodiment, cache replacement logic performs a selection of a line of cache for data eviction, where the selection is in response to the policy unit providing an indication of the determined parameter value.

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Barcelona, Spain

Blas Cuesta