Taiwan Semiconductor Manufacturing Comp. Ltd.

Blanka Magyari-Kope

Ying-Chih Chen

Sai-Hooi Yeong

Yu-Ming Lin

Chung-Te Lin

Bo-Feng Young

Chun-Chieh Lu

Tzer-Min Shen

Yu-Chuan Shih

Qing Shi

Ashwathi Iyer

Chris Liu

Jiamin Wang

A device includes a gate stack and a channel layer over the gate stack. The gate stack includes a metal gate electrode, a ferroelectric layer, and a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode. The semiconducting oxide layer has a thickness between approximately 1 μm and approximately 30 μm.

Semiconductor device, ferroelectric capacitor and laminated structure

A semiconductor device includes a first electrode layer, a ferroelectric layer, and a second electrode layer. A material of the ferroelectric layer comprises a ferroelectric material doped with a first dopant and a second dopant different from the first dopant, and the first dopant comprises cerium. The ferroelectric layer is disposed between the first electrode layer and the second electrode layer.

Semiconductor devices having ferroelectric tunnel junction structure

A semiconductor device includes a first electrode layer, a ferroelectric layer, a first alignment layer and a second electrode layer. A material of the first alignment layer includes rare-earth metal oxide. The ferroelectric layer and the first alignment layer are disposed between the first electrode layer and the second electrode layer, and the first alignment layer is disposed between the ferroelectric layer and the first electrode layer.

Semiconductor devices including FTJ structure

A semiconductor structure includes, from bottom to top or from top to bottom, a gate electrode, a ferroelectric dielectric layer, a metal-rich metal oxide layer, a dielectric metal nitride layer, and a metal oxide semiconductor layer. A ferroelectric field effect transistor may be provided by forming a source region and a drain region on the metal oxide semiconductor layer. The metal-rich metal oxide layer and the dielectric metal nitride layer homogenize and stabilize the interface between the ferroelectric dielectric layer and the metal oxide semiconductor layer, and reduce excess oxygen atoms at the interface, thereby improving switching characteristics of the ferroelectric field effect transistor.

Interfacial dual passivation layer for a ferroelectric device and methods of forming the same

A semiconductor device includes a gate stack and a channel layer over the gate stack. The gate stack includes a metal gate electrode, a ferroelectric layer, and a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode. The semiconducting oxide layer includes SrRuO, InGaZnO (IGZO) or LaSrMnO.

A semiconductor device includes a substrate, a gate stack over the substrate, a channel layer over the gate stack, and a source/drain electrode. The gate stack includes a metal gate electrode, a ferroelectric layer, and a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode. The source/drain electrode is formed on the channel layer and disposed on sides of the gate stack.

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Hsinchu, Taiwan

Blanka Magyari-Kope