Nortel Networks Corporation

Ciena Corporation

Blake Toplis

Todd D Morris

Eric Maniloff

Ronald Joseph Gagnon

Timothy James Creasy

Stacy W Nichols

David G Stuart

Norman Allan Lyon

James St Leger Harley

Tung Trong Nguyen

Markus Wandel

A method at a receiver comprises receiving a signal conveying symbols at respective positions within a clock cycle, the symbols comprising a data set consisting of data symbols and a pilot set consisting of pilot symbols; determining detected phases of the symbols based on the signal; generating first phase estimates based on the detected phases of a subset of the pilot set, and reference phases of the subset of the pilot set, the first phase estimates being associated with the positions of the pilot set; and generating second phase estimates based on the detected phases of the pilot set, reference phases of the pilot set, and the first phase estimates, the second phase estimates being associated with the positions of the pilot set and of at least a subset of the data set; and applying rotations to the detected phases of the symbols based on the second phase estimates.

Modular carrier recovery

An apparatus and a method for sender-initiated credit recovery in a closed-loop credit based flow control system, includes assigning a number of credits to a sender unit in the credit based flow control system. The method also includes decrementing a credit count in the sender unit in response to the sender sending data to the receiver and incrementing the credit count in the sender unit in response to receiving returned credits from the receiver unit. The method also includes determining if a loss or gain in the number of credits in the credit based flow control system has occurred and adjusting the credit count based on the determined loss or gain.

Credit recovery in a credit based flow control system

Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained.

Method and apparatus for aligning multiple outputs of an FPGA

A node in a packet network such as an ATM network receives a plurality of traffic classes and outputs them to an output link. The invention relates to a technique of scheduling the traffic classes in a time linked fashion at the node based on the bandwidth allocated to each traffic class. Traffic scheduling based strictly on priority may not satisfy delay and loss guarantees of traffic classes when there are many classes with many different priority levels. The rate based scheduling in a time-linked fashion solves these problems by limiting the bandwidth to which each class is accessible. According to one embodiment, the invention uses timeslot values and a linked list of the traffic classes.

Time linked scheduling of cell-based traffic

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Ottawa, Canada

Blake Toplis