International Business Machines Corporation

Globalfoundries Inc.

Blake G Fitch

Robert S Germain

Michael C Pitman

Michele M Franceschini

Todd Edward Takken

Mark Edwin Giampapa

Steven R Abrams

Daniel Christopher Worledge

Julia Elizabeth Rice

Hans Werner Horn

William Clarence Swope

Maria Eleftheriou

Thomas Ward

John K Debrosse

Aleksandr Rayshubskiy

Wolfgang Huber

Aleksandr Rayshubskly

Ashish Jagmohan

Thomas James Christopher Ward

Lars Schneidenbach

Michael G Pitman

Dror Gershon Feitelson

John Kenneth DeBrosse

Daniel Michael Kuchta

Douglas James Joseph

Jeannine Madelyn Trewhella

Glen Walden Johnson

Bernard Metzler

Sandra Johnson Baylor

Peter Frank Corbett

Aleksandr Rayshubakly

Bernaard Metzler

T J Chris Ward

A supercomputer comprising a memory device and a plurality of interconnected hardware processors capable of performing parallel processing is coupled to a mainframe computer comprising one or more hardware processors. The supercomputer functions as a part of the mainframe computer's memory hierarchy.

Replacing mechanical/magnetic components with a supercomputer

A method for memory management includes streaming bits to a memory buffer on a memory device using a write data channel that optimizes a speed of writing to the memory devices. The bits are written to non-volatile memory cells in the memory device at a first speed, using a bi-directional bus. Bits are read from the memory device over a read channel to provide reads at a second speed that is slower than the first speed, using the bi-directional bus.

Nonvolatile memory interface for metadata shadowing

A memory includes multiple non-volatile memory devices, each having multiple nonvolatile memory cells. A write controller is configured to stream bits to the memory devices using a write data channel that optimizes a speed of writing to the memory devices to provide writes at a first speed. A read controller is configured to read bits from the memory devices, at a second speed slower than the first speed, using a read channel. A bi-directional bus that both the write controller and the self-referenced read controller share to access the plurality of non-volatile memory devices.

A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.

A queued, byte addressed system and method for accessing flash memory and other non-volatile storage class memory, and potentially other types of non-volatile memory (NVM) storage systems. In a host device, e.g., a standalone or networked computer, having attached NVM device storage integrated into a switching fabric wherein the NVM device appears as an industry standard OFED&#x2122; RDMA verbs provider. The verbs provider enables communicating with a 'local storage peer' using the existing OpenFabrics RDMA host functionality. User applications issue RDMA Read/Write directives to the 'local peer (seen as a persistent storage) in NVM enabling NVM memory access at byte granularity. The queued, byte addressed system and method provides for Zero copy NVM access. The methods enables operations that establish application private Queue Pairs to provide asynchronous NVM memory access operations at byte level granularity.

Local direct storage class memory access

Persistent data storage is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

Low latency and persistent data storage

A field-based similarity search system includes an input device which inputs a query molecule, and a processor which partitions a conformational space of the query molecule into a fragment graph including an acyclic graph including plural fragment nodes connected by rotatable bond edges, computes a property field on fragment pairs of fragments of the query molecule from the fragment graph, the property field including a local approximation of a property field of the query molecule, constructs a set of features of the fragment pairs based on the property field, the features including a set of local, rotationally invariant, and moment-based descriptors generated from all conformations of the fragment graph of the query molecule, and weights the descriptors according to importance as perceived from a training set of descriptors to generate a context-adapted descriptor-to-key mapping which maps the set of descriptors to a set of feature keys.

Field-based similarity search system and method

Persistent data storage is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

Techniques are disclosed for creating a load balanced spatial partitioning of a structured, diffusing system of particles. An exemplary method includes steps of determining a subset of a set of nodes within a given portion of the coordinate system intersected by a surface defined by points having a given distance from the surface of the given node; and mirroring the determined subset to at least another portion of the coordinate system.

Creating a load balanced spatial partitioning of a structured, diffusing system of particles

An information processing system for performing a transform of a multidimensional matrix in a distributed memory network. The method includes storing a multidimensional matrix of side N in a distributed memory network with a plurality of nodes and distributing work associated with a calculation of a transform of the matrix among Nof the plurality of nodes. The system further includes a receiver for receiving results of the calculation of the transform of the matrix by the nodes.

Multi-dimensional transform for distributed memory network

A computer readable storage medium for performing a transform of a multidimensional matrix in a distributed memory network by: storing a multidimensional matrix of side N in a distributed memory network with a plurality of nodes and distributing work associated with a calculation of a transform of the matrix among Nof the plurality of nodes. The medium further receives results of the calculation of the transform of the matrix by the nodes.

Growing community of inventors

New Rochelle, NY, United States of America

Blake G Fitch