Intel Corporation

Other

Blaise B Fanning

Mikal Hunsaker

Sridhar Lakshmanamurthy

Michael T Klinglesmith

Robert P Adler

David J Harriman

Jasmin Ajanovic

David M Lee

Joseph Murray

Eran Tamari

Rohit R Verma

Raymond Scott Tetrick

Shekoufeh Qawami

Robert J Royer, Jr

Frank T Hady

Mark A Schmisseur

James B Crossland

Eng Hun Ooi

David B Minturn

Daniel Greenspan

Toby Opferman

Shane Matthews

Rajesh Sundaram

David Zimmerman

Jeffrey R Wilcox

Leena K Puthiyedath

Mohan Nair

Kar Leong Wong

Yoav Lossin

Gary J Lavelle

Joydeep Ray

Ravishankar Iyer

Ioannis T Schoinas

Daniel Cutter

Michael W Williams

Jose Niell

Asaf Rubinstein

Ramadass Nagarajan

Ritesh B Trivedi

Eric R Wehage

Marc D Torrant

Buck Gremel

Anil K Sabbavarapu

Wayne Moore

Ken Creta

Altug Koker

Vincent J Zimmer

Michael A Rothman

Glenn J Hinton

Debra Bernstein

Raj K Ramanujan

David M Puffer

Aravindh V Anantaraman

Rajesh Bhikhubhai Patel

Shlomo Raikin

Joseph A Bennett

Alaa R Alameldeen

Aditya Sreenivas

Belliappa Manavattira Kuttanna

Ashish V Choubal

Kenneth D Shoemaker

Zvika Greenfield

Lance E Hacking

Julius Yuli Mandelblat

Bryan R White

Bruce L Fleming

Nagi Aboulenein

Todd M Witter

Ravi Kolagotla

Ramana V Rachakonda

Ariel Berkovits

Eugene P Matter

Eran Shifer

Binta M Patel

Deepak Limaye

Quang T Le

James J Greensky

Evgeny Bolotin

Neil Schaper

Khong S Foo

Dannie G Feekes

Mikal C Hunsaker

Mohan K Nair

Tony Opferman

Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.

Techniques to configure a solid state drive to operate in a storage mode or a memory mode

Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

Multi-level memory with direct access

A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment comprises: a level N cache to store a first plurality of entries; a level N+1 cache to store a second plurality of entries; the level N+1 cache to initially be provided with responsibility for implementing a least recently used (LRU) eviction policy for a first entry until receipt of a request for the first entry from the level N cache at which time the entry is copied from the level N+1 cache to the level N cache, the level N cache to then be provided with responsibility for implementing the LRU policy until the first entry is evicted from the level N cache, wherein upon being notified that the first entry has been evicted from the level N cache, the level N+1 cache to resume responsibility for implementing the LRU eviction policy.

Apparatus and method for shared least recently used (LRU) policy between multiple cache levels

Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

Memory latency management

Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.

Adaptive configuration of non-volatile memory

An apparatus is described. The apparatus includes a memory controller to interface with a multi-level system memory. The memory controller includes a pinning engine to pin a memory page into a first level of the system memory that is at a higher level than a second level of the system memory.

Method and apparatus for pinning memory pages in a multi-level system memory

In one embodiment, the present invention is directed to method for receiving a packet in a first agent, where the packet includes a first packet header with an expanded header indicator. Based on this indicator, the agent can determine if the packet includes one or more additional packet headers. If so, the agent can next determining if it supports information in the additional packet header based on a header identifier of the additional header. Other embodiments are described and claimed.

Sending packets with expanded headers

A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment of the invention comprises: a level N cache to store a first plurality of entries; a level N+1 cache to store a second plurality of entries; the level N+1 cache to initially be provided with responsibility for implementing a least recently used (LRU) eviction policy for a first entry until receipt of a request for the first entry from the level N cache at which time the entry is copied from the level N+1 cache to the level N cache, the level N cache to then be provided with responsibility for implementing the LRU policy until the first entry is evicted from the level N cache, wherein upon being notified that the first entry has been evicted from the level N cache, the level N+1 cache to resume responsibility for implementing the LRU eviction policy with respect to the first entry.

Systems, apparatuses and methods may provide for identifying a first block and a second block, wherein the first block includes a first plurality of cache lines, the second block includes a second plurality of cache lines, and the second block resides in a memory-side cache. Additionally, each cache line in the first plurality of cache lines may be compressed with a corresponding cache line in the second plurality of cache lines to obtain a compressed block that includes a third plurality of cache lines. In one example, the second block is replaced in the memory-side cache with the compressed block if the compressed block satisfies a size condition.

Replacement of a block with a compressed block to increase capacity of a memory-side cache

A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.

System for configuring partitions within non-volatile random access memory (NVRAM) as a replacement for traditional mass storage

Technology for an apparatus is described. The apparatus can include a plurality of cache memories and a cache controller. The cache controller can allocate a cache entry to store data across the plurality of cache memories. The cache entry can include a value in a metadata field indicating an interleave policy. The cache controller can selectively assign the interleave policy to be applied based on a type of data stored in the plurality of cache memories.

Selevtive application of interleave based on type of data to be stored in memory

A non-volatile random access memory (NVRAM) is used in a computer system to provide instant responses to sleep state transitions. The computer system includes a processor coupled to an NVRAM, which is accessible by the processor without passing through an I/O subsystem. The NVRAM is byte-rewritable and byte-erasable by the processor. In response to a request to enter a powered sleep state, the computer system converts the powered sleep state into a powered-off sleep state with system memory context stored in the NVRAM. The powered sleep state is defined as a state in which power is supplied to volatile random access memory in the computer system, and the powered-off sleep state is defined as a state in which power is removed from the volatile random access memory. In response to a wake event, the computer system resumes working state operations using the system memory context stored in the NVRAM.

Method and system for providing instant responses to sleep state transitions with non-volatile random access memory

Growing community of inventors

Cameron Park, CA, United States of America

Blaise B Fanning