Intel Corporation

Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Blaine Stackhouse

Kevin Safford

Rohit Bhatia

Chris Bostak

Steve Undy

Richard Blumberg

John J Wuu

Donald R Weiss

Terry L Lyon

Shawn Kenneth Walker

Gordon W Motley

Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

Methods and apparatuses for reducing step loads of processors

The present invention employs a bias voltage having a selectable magnitude to bias a weak write pull-down transistor in a write driver of a static random access memory (SRAM) array. A programmable weak write test mode (PWWTM) bias generator includes an output signal that is a logic high in a default mode when a WWTM is not active. When the WWTM is active, the generator output signal is the bias voltage having the selectable magnitude. The default mode logic high is actively maintained when the generator output is connected to a load, such as the write driver of the SRAM array. A WWTM-enabled SRAM system includes the PWWTM bias generator. A method of driving a WWTM-equipped SRAM includes generating and applying the output signal to a gate of a weak write pull-down transistor of the SRAM array write driver in the default mode and the WWTM.

Programmable weak write test mode (PWWTM) bias generation having logic high output default mode

A source cache transfers data to an intermediate cache along a data connection. The intermediate cache is provided between the source cache and a target, and includes a memory array. The source cache may also transfer data to the target along the data connection while bypassing the memory array of the intermediate cache.

Cache connection with bypassing feature

Among other things, the present invention provides an improved decoder section with a noise resistant input. In one embodiment, the section includes a ratioed gate and a stack with at least one transistor. The ratioed gate has an input for receiving a first input signal, which may be noisy, from one or more input signals and an output that generates a true value, when the gate is activated, if the first input signal is true. The stack with at least one transistor is operably connected to the ratioed gate. It has at least one input for receiving the remaining one or more input signals apart from the first input signal. When these remaining input signals are true, the stack activates the ratioed gate. Otherwise, if any of the remaining signals are false, it inactivates the gate. Accordingly, the ratioed gate generates a true output when all of the one or more inputs are true.

General purpose decode implementation for multiported memory array circuits

An ESD protection system for protecting a CMOS integrated circuit (IC) with multiple power supplies is provided. The ESD protection system uses on-chip diodes to route ESD current from a first IC pin to the main positive power supply, where it is partly absorbed by the parasitic capacitance between the positive supply and ground. A charge sharing diode is provided between the main power supply and the clean power supply networks so that more of the ESD current may be absorbed by the parasitic capacitance between the clean power supply networks and ground. A core shunt circuit, which turns on when an ESD event is sensed, is provided to directly shunt ESD current from the positive supply to ground. Another diode is used to route current from the ground network out a second IC pin.

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Fort Collins, CO, United States of America

Blaine Stackhouse