Hewlett-Packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Hewlett-Packard Company

Western Digital Technologies, Inc.

Blaine Douglas Gaither

Benjamin Daniel Osecky

Bret Alan McKee

Russ William Herrell

Judson Eugene Veazey

Gregg Bernard Lesartre

Dale Calvin Morris

Robert J Brooks

Andrew Ray Wheeler

Patrick Knebel

Verna Knapp

John A Morrison

Gregory William Thelen

David Fisk

Kathryn A Evertson

Gary Belgrave Gostin

Darel N Emmot

Robert B Smith

Lidia Warnes

Eric M Rentschler

Jerome C Huck

Gerald J Kaufman, Jr

Douglas Vincent Larson

Carey Huscroft

John R Feehrer

Richard Glen Fowles

David A Plettner

Donna E Ott

Greg B Lesartre

Michael J Mahon

Mark V Riley

Benjamin D Osecky

A system and method for addressing split modes of persistent memory are described herein. The system includes a non-volatile memory comprising regions of memory, each region comprising a range of memory address spaces. The system also includes a memory controller (MC) to control access to the non-volatile memory. The system further includes a device to track a mode of each region of memory and to define the mode of each region of memory. The mode is a functional use model.

Split mode addressing a persistent memory

A technique includes receiving an alert indicator in a distributed computer system that includes a plurality of computing nodes coupled together by cluster interconnection fabric. The alert indicator indicates detection of a fault in a first computing node of the plurality of computing nodes. The technique indicates regulating communication between the first computing node and at least one of the other computing nodes in response to the alert indicator to contain error propagation due to the fault within the first computing node.

Controlling error propagation due to fault in computing node of a distributed computing system

In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Reflective memory bridge for external computing nodes

A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.

Fault tolerance for persistent main memory

Systems and methods for utilizing probabilistic data structures to handle interrogations regarding whether or not objects might be stored in an object store of an object storage device are disclosed. More particularly, a controller of an object storage device includes control circuitry and a memory operative to store a probabilistic data structure. The probabilistic data structure has data related to the presence of data in an object store of the object storage device. The control circuitry is configured to receive an interrogation from a computing device for an object; utilize the probabilistic data structure to determine that the object is possibly stored in the object store or definitely not stored in the object store; and in response to a determination that the object is definitely not stored in the object store, respond to the interrogation that the object is not stored in the object store.

Object storage device with probabilistic data structure

Techniques for updating data in a reflective memory region of a first memory device are described herein. In one example, a method for updating data in a reflective memory region of a first memory device includes receiving an indication that data is to be flushed from a cache device to the first memory device. The method also includes detecting a memory address corresponding to the data is within the reflective memory region of the first memory device and sending data from the cache device to the first memory device with a flush operation. Additionally, the method includes determining that the data received by the first memory device is modified data. Furthermore, the method includes sending the modified data to a second memory device in a second computing system.

Implementing coherency with reflective memory

A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.

Cache and method for cache bypass functionality

A method of determining an estimated data throughput capacity for a computer system includes the steps of creating a first model of data throughput of a central processing subsystem in the computer system as a function of latency of a memory subsystem of the computer system; creating a second model of the latency in the memory subsystem as a function of bandwidth demand of the memory subsystem; and finding a point of intersection of the first and second models. The point of intersection corresponds to a possible operating point for said computer system.

Managing workload distribution among computer systems based on intersection of throughput and latency models

A processor transmits clean castout messages indicating that a cache line is not dirty and is no longer being stored by a lowest level cache of the processor. An external cache receives the clean castout messages and manages cache lines based in part on the clean castout messages.

External cache operation based on clean castout messages

A method for providing a transactional memory is described. A cache coherency protocol is enforced upon a cache memory including cache lines, wherein each line is in one of a modified state, an owned state, an exclusive state, a shared state, and an invalid state. Upon initiation of a transaction accessing at least one of the cache lines, each of the lines is ensured to be either shared or invalid. During the transaction, in response to an external request for any cache line in the modified, owned, or exclusive state, each line in the modified or owned state is invalidated without writing the line to a main memory. Also, each exclusive line is demoted to either the shared or invalid state, and the transaction is aborted.

Transactional cache memory system

Provided is a method for uniquely masking addressing to the cache memory for each user, thereby reducing risk of a timing attack by one user on another user. The method comprises assigning a first mask value to the first user and a second mask value to the second user. The mask values are unique to one another. While executing a first instruction on behalf of the first user, the method comprises applying the first mask value to set selection bits in a memory address accessed by the first instruction. While executing a second instruction on behalf of the second user, the method comprises applying the second mask value to set selection bits in the memory address accessed by the second instruction. The result offers an additional level of security between users as well as reducing the occurrence of threads or processes contending for the same memory address.

Address masking between users

Examples disclosed herein relate to determining whether a right to use memory modules in a reliability mode has been acquired. Examples include determining whether the right to use a plurality of memory modules in a reliability mode has been acquired, if a performance mode is selected for operation of the plurality of memory modules.

Determining whether a right to use memory modules in a reliability mode has been acquired

A first processing element can run within a first operating range. A second processing element can run within a second operating range. A third processing element can be activated if the second processing element fails or can be refrained from being run unless the first or second processing element fails.

Growing community of inventors

Fort Collins, CO, United States of America

Blaine Douglas Gaither