International Business Machines Corporation

Bjorn P Christensen

Kevin Franklin Reick

Nathaniel R Chadwick

Jon Robert Tetzloff

James M Crafts

Allen R Hall

Dung Q Nguyen

Joel Abraham Silberman

William Elton Burky

Victor V Zyuban

Mary Douglass Brown

Robert Allen Cordes

David Andrew Schroter

Maureen Anne Delaney

Saiful Islam

Sam G Chu

Albert Thomas Williams

Jafar Nahidi

A method for facilitating adaptive frequency in a processor having a plurality of cores. The method can include conducting tests on the processor; determining, via the processor testing system, default parameters for operating one or more of the cores, wherein the default parameters are based on results of the tests and cause one or more of the cores to operate within production yield goals of the processor; determining alternative parameters for operating one or more of the cores, wherein the alternative parameters are based on results of the test and cause one or more of the cores to operate outside production yield goals of the processor, and wherein the alternative parameters are usable to reconfigure one or more of the cores after an initial operation per the default parameters; and writing the default parameters and the alternative parameters to a production data storage of the processor.

Adaptive frequency optimization in processors

A processor can have a plurality of cores. A first core processor of a first core can read one or more values of a default parameter set. The first core can be operated in accordance with a first operating characteristic based, at least in part, on the one or more values of the default parameter set. The first core processor can receive an indication to change the operating characteristic of the first core processor. In response to receiving the indication to change the operating characteristic, a signal can be issued to the first core processor to reset. In response to the reset, the first core processor can read one or more values of an alternative parameter set. The first core processor can then be operated in accordance with a second operating characteristic based, at least in part, on the one or more values of the alternative parameter set.

The embodiments described herein relate to dynamically detecting a frequency change condition for microprocessor performance. An instruction is received, and a frequency change condition associated with the received instruction is dynamically detected. A frequency modulation is performed in response to the dynamic detection. The frequency modulation includes selecting a second frequency for optimal instruction processing different from a first frequency, the first frequency being a default operating frequency of the microprocessor. Execution of the instruction is completed at the second frequency. Accordingly, incoming execution instructions are logically analyzed, and the processor frequency is selectively modified based on associated instruction conditions.

Dynamic workload frequency optimization

A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.

Dependency matrix with reduced area and power consumption

A circuit and method provide rename register reallocation for simultaneous multi-threaded (SMT) processors that redistributes rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. The internal control logic then signals the resources to reallocate the resources. Rename resources are reallocated by directing an action at the rename mapper. When switching from SMT to ST mode, the mapper is directed to drop entries for the dying thread, but on a switch from ST to SMT mode, 'dummy' instruction group dispatch indications are sent to the mapper that indicate use of all architected registers for each thread.

Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor

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Round Rock, TX, United States of America

Bjorn P Christensen