Cadence Design Systems, Inc.

Björn Håkan Hjort

Lars Lundgren

Habeeb Farah

Ahmad S Abo Foul

Chung-Wah Norris Ip

Ziyad Hanna

Fabiano Cruz Peixoto

Craig Franklin Deaton

Kathryn Drews Kranen

Paula Selegato Mathias

Breno Rodrigues Guimarães

Caio Araujo Teixeira Campos

Benjamin Chen

Eran Talmor

A method for assertion-based formal verification includes executing a plurality of formal verification regression runs on a model of an electronic design; for each of the regression runs, using a unique signature function, calculating and saving a unique signature value for each instantiation of a property of a plurality of properties of the model of the electronic design and a status result for that instantiation of the property in that regression run; and signing off a current version of the model of the electronic device and presenting as a status result for each the instantiations of a plurality of the properties of the current version of the model of the electronic design the preferred status result obtained for that instantiation of the property per the same unique signature value that was calculated for that instantiation of the property in previous runs of the plurality of formal verification regression runs.

Method and system for assertion-based formal verification using unique signature values

The present disclosure relates to a system and method for assertion-based formal verification in an electronic design environment. Embodiments may include executing, using a processor, an assertion-based formal verification proof process on a model of an electronic design and analyzing a first property associated with the model. Embodiments may further include generating at least one trace of the first property and determining a mapping function associated with the first property. Embodiments may also include storing the at least one trace and the mapping function. Embodiments may further include determining that a second property associated with the model shares a cone of influence with the first property and generating a new trace based upon, at least in part, the mapping function.

System and method for assertion-based formal verification using cached metadata

The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, at least one electronic design file and a set of inputs from a user, wherein the at least one electronic design file and set of inputs are associated with an electronic design. Embodiments may further include performing formal verification on at least a portion of the electronic design and determining, using a model checker, one or more conflicts associated with a variable during the formal verification. Embodiments may also include translating the one or more conflicts into one or more corresponding signal names and displaying, at a graphical user interface, the corresponding signal names.

System, method, and computer program product for providing feedback during formal verification

Disclosed is an improved approach to implement selective transformations of circuit components for performing verification. The approach looks at the observability of components to downstream properties to determine whether transformations are needed. The verification system leverages the knowledge about the behavior of the domains/components to identify only a subset of components that really need to undergo transformation.

Method and system for implementing selective transformation for low power verification

A model checking tool, which is used to test a circuit design, attempts to reach a target state from an initial state in the state-space of the circuit design using one or more intermediate states. Through an iterative process, the tool identifies intermediate states in the state-space of the circuit design that are used to generate starting states for subsequent iterations of the process. The intermediate states help to restrict the scope of the state-space search to reduce the time and memory requirements needed to reach the target state. The model checking tool also explores the state-space in parallel from a subset of computed restart states, which reduces the possibility of bypassing any essential intermediate or target states.

Guided exploration of circuit design states

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Göteborg, Sweden

Björn Håkan Hjort