Samsung Electronics Co., Ltd.

Biwoong Chung

Junjin Kong

Namshik Kim

Tae-Hwan Kim

Kui-Yon Mun

Youngkwang Yoo

Jaegeun Park

Daewook Kim

A storage device is provided which includes an ECC circuit. At a write operation, the ECC circuit generates a CRC (cyclic redundancy check) parity corresponding to data and generates an ECC (error correction code) parity corresponding to the data using an error correction code. At a read operation about the data stored in the at least one nonvolatile memory device, the ECC circuit corrects an error of the data using the CRC parity and the ECC parity.

Memory controller, storage device including the same and data encoding and decoding methods thereof

A storage system is provided which includes: a storage device including a first memory, which may be nonvolatile memory, and a second memory, which may be a device memory, and configured to request a test on at least one of the first and second memories; and a host configured to test the at least one memory in response to the request for the memory test from the storage device and store the test result in the first memory or a third memory.

Storage system managing run-time bad cells

Methods of reading data from storage devices may include reading data stored in the storage device using normal read voltages; performing a first low density parity check (LDPC) decoding based on the read data; generating reliability bits of each of read bits according to the decoding result, the read bits being bits of the read data; and performing a second low density parity check (LDPC) decoding based on the read data and the reliability bits to perform a first error correction on the read data.

Method of reading data from storage device, error correction device and storage system including error correction code decoder

Growing community of inventors

Yongin-si, South Korea

Biwoong Chung