Intel Corporation

Bishara Shomar

Hong Jiang

Ronny Ronen

Thomas A Piazza

Val Gene Cook

Michael K Dwyer

Dinakar Munagala

Gregory Pribush

Evgeni Krimer

A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.

Dataport and methods thereof

According to one aspect of the invention, a method is provided in which a current instance of an instruction is received. The current instance of the instruction contains a reference to a logical floating point register. A first rename phase is performed to convert the current's instance reference to the logical floating point register into a reference to an absolute register. A second rename phase is performed in parallel with the first rename phase to convert the reference to the absolute register into a reference to a physical register, based upon results obtained from performing the first rename phase with respect to a previous instance of the instruction.

Method and apparatus for fast, speculative floating point register renaming

A device is presented including a processor. A local memory is connected to the processor. The processor includes a hot way cache accessing process. A method is presented that includes accessing a memory. The method includes processing a first plurality of memory cells and a second plurality of memory cells in the memory. The method determines if a memory block is a last recently accessed memory block. The method determines whether a memory block accessed is a hit or a miss. The method accesses a lower memory level if the memory block accessed is a miss. Also, processing the second plurality of memory cells for an exact block if the block accessed is a hit but not the last recently accessed memory block. And, providing the memory block for additional access if the memory block accessed is a hit and is a last recently accessed memory block.

Hot way caches: an energy saving technique for high performance caches

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Nazareth, Israel

Bishara Shomar