International Business Machines Corporation

Birgit Schubert

Derek E Williams

Viresh Paruthi

Michael Stephen Floyd

Wolfgang Roesner

Stephen Gerard Shuma

Michael Sperling

Benedikt Geukes

Ali S El-Zein

Stephen J Barnfield

Klaus-Dieter Schubert

Ann H Chen

A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.

Clock mapping in an integrated circuit design

A successive approximation analog-to-digital converter (SA-ADC) includes a reference generator configured to output a first voltage and a second voltage; a comparator, the comparator having a positive input and a negative input thereto, the comparator being configured to receive the first voltage and the second voltage; and a comparator input toggle located between the reference generator and the comparator, wherein the comparator input toggle is configured to receive the first and second voltages from the reference generator and provide the first and second voltages to the comparator, wherein the comparator input toggle is further configured to switch between a first position, in which the first voltage is connected to the positive input, and the second voltage is connected to the negative input, and a second position, in which the second voltage is connected to the positive input, and the first voltage is connected to the negative input.

Successive approximation analog to digital converter with comparator input toggling

Growing community of inventors

Boeblingen, Germany

Birgit Schubert