Nxp USA, Inc.

Freescale Semiconductor,inc.

Nxp B.v.

Nxp USA, Inx.

Birama Goumballa

Didier Salle

Cristian Pavao Moreira

Olivier Vincent Doare

Cristian Pavao-Moreira

Yi Yin

Dominique Delbecq

Gilles Montoriol

Pierre Pascal Savary

Olivier Vincent Doaré

Jean-Stephane Vigier

Achal Venkatesh

Baptiste Barroué

Olivier Tico

Julien Orlando

Matthis Bouchayer

Stephane Dugalleix

Stephane Thuriés

Cristian Pavao-Moriera

An integrated circuit includes a functional circuit and a power calibration and monitoring system including a digital-to-analog converter (DAC), a variable gain amplifier (VGA), and a counter. The DAC generates a differential pair of feedback currents based on a digital count. The VGA generates a differential pair of amplified signals based on a magnitude difference between the differential pair of feedback currents and a differential pair of detection currents derived from a differential pair of node voltages associated with the functional circuit. The counter generates the digital count based on the differential pair of amplified signals. The differential pair of feedback currents is controlled such that the magnitude difference between the differential pair of detection currents and the differential pair of feedback currents is within a tolerance limit. A power associated with the functional circuit is calibrated and monitored based on the digital count.

Power calibration and monitoring system

A power amplifier stage including multiple amplifier branch circuits, in which each amplifier branch circuit includes a cascode device, a source device, and a replica cascode device. The cascode device has current terminals coupled between an output node and an intermediate node, and has a control terminal receiving a corresponding activation signal. The source device has current terminals coupled between a supply reference node and the intermediate node, and has a control terminal receiving an input signal. The replica cascode device has current terminals coupled between a supply node and the intermediate node, and has a control terminal receiving a corresponding complementary activation signals. An output power level of the power amplifier stage is controlled by asserting a selected number of activation signals and corresponding complementary activation signals for activating a selected number of the amplifier branch circuits.

Current steering biasing for power control in cascode-based power amplifier stage of radar applications for improved reliability

A first input signal that corresponds to an output transmitted signal of an amplifier of a vehicle radar system is received and a digital threshold signal is transmitted to an input terminal of a digital-to-analog converter. The digital-to-analog converter is configured to generate an analog threshold value that is at least partially determined by a digital threshold value encoded into the digital threshold signal. If it is determined that a magnitude of the first input signal is less than a magnitude of the analog threshold value, a flag signal is transmitted to a system controller. The flag signal is indicative that a power level of the first output signal has fallen below a safety threshold value.

Time-continuous power monitoring for radar applications

A method, device and a radar system for determining phase error caused by impairments in a phase rotator comprises (a) forcing the Q path of the phase rotator to zero and obtaining a first sequence of successive measurement values, (b) forcing the I path of the phase rotator to zero and obtaining a second sequence of successive measurement, (c) forming a sequence of successive measurement value pairs, each measurement value pair comprising one measurement value from the first sequence of successive measurement values and one measurement value from the second sequence of successive measurement values (d) calculating an actual phase value for each of the successive measurement value pairs, and (e) determining the phase error by comparing the actual phase values with the corresponding reference phase values.

Method, device, and radar system

A signal coupler () comprising: a main-transmission-line () that extends in a longitudinal direction within a substrate () between an input port and an output port; and a coupled-transmission-line () that extends in the longitudinal direction within the substrate () between a coupled port and a termination port. The coupled-transmission-line () is in a second layer (). The main-transmission-line () comprises a first-portion () in a first layer (), a second-portion () in a second layer (), and a third-portion () in a third layer (). At least part of the first-portion () is spaced apart from the coupled-transmission-line () in a depth direction. At least part of the second-portion () is spaced apart from the coupled-transmission-line () in the depth direction. At least part of the third-portion () is spaced apart from the coupled-transmission-line () in the depth direction.

Signal coupler

The disclosure relates to a radar transceiver having a transmitter comprising a phase shifter. Example embodiments include a radar transceiver () having a normal mode of transmitter operation and a self-test mode of operation, the transceiver () comprising: a digital controller () configured to provide a digital control signal indicative of a phase shift; a digital to analogue converter () configured to receive the digital control signal and provide an analogue signal in accordance with the phase shift; a phase shifter () configured to receive the analogue signal and provide a phase shifted output signal for transmission; a dummy load () connected to receive the analogue signal from the digital to analogue converter () and to provide an analogue output; a resistor network () connected across an output of the dummy load (); a testing module () configured to measure the analogue output of the dummy load (); and a controller module () configured to control operation of the dummy load (), testing module () and digital controller () during the self-test mode of operation by: enabling the dummy load (); operating the digital controller () to provide a range of digital control signals to the digital to analogue converter (); and operate the testing module () to measure the analogue output of the dummy load () to determine a measure of linearity of the digital to analogue converter ().

Radar transceiver

A frequency synthesizer is described that includes: a voltage controlled oscillator, VCO; a VCO bias circuit, operably coupled to the VCO and configured to provide a controllable bias current of the VCO; a temperature sensor, located in the frequency synthesizer, configured to determine an operating temperature of the frequency synthesizer; an analog-to-digital converter, ADC, operably coupled to the temperature sensor and configured to provide a digital representation of the determined operating temperature; and a bias control circuit operably coupled and configured to provide a bias control signal to the VCO bias circuit based on the determined operating temperature of the frequency synthesizer. The VCO bias circuit is configured to adjust the controllable bias current applied to the VCO based on the bias control signal.

Frequency synthesizer with phase noise temperature compensation, communication unit and method therefor

A communication unit () is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit () configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (); and transmit the modulated master-slave clock signal () to the at least one slave device. The at least one slave device comprises a demodulator circuit () configured to: receive and demodulate the modulated master-slave clock signal (); and re-create therefrom the system clock signal () and the frame start signal ().

Communication unit and method for clock distribution and synchronization

A circuit () for testing failure of a connection between a radio frequency, RF, integrated circuit () and external circuitry (), the circuit comprising: an amplifier () having first and second input paths () and first and second output paths (); a first power detector () coupled to one of said first or second output paths; at least one connection () between said first and second output paths () and said external circuitry (), connecting said outputs to a RF combiner () said external circuitry; at least one disabling circuit () coupled to at least one of said first and second output paths () or at least one of said first and second input path (), before said path reaches said power detector (); for disabling one of said inputs or outputs; wherein when said input or output path is disabled (), and a signal is output along the enabled output path (), the power detector () on said disabled output path can detect if there is a failure in said at least one connection ().

Embedded test circuitry and method therefor

The present application relates to a differential Colpitts voltage-controlled oscillator (VCO) circuit, which comprises a pair of transistors with control terminals biased by a common biasing voltage and a pair of couplers arranged to cross-couple corrector/drain of the transistors and the base/gate of the differential transistors. The pair of couplers have a coupling factor k, which used to enhance the transconductance of the transistor pair, therefore can be used for power consumption reduction and phase noise minimalization.

Differential voltage-controlled (VCO) oscillator

The disclosure relates to voltage-controlled-oscillator circuit comprising: a charge-pump configured to generate a tuning-voltage, the tuning-voltage having a minimum-operating-voltage; an offset-voltage-source configured to generate an offset-voltage in accordance with the minimum-operating-voltage; and a voltage-controlled-oscillator, VCO, configured to provide an oscillator frequency in accordance with the tuning-voltage and the offset-voltage.

Voltage-controlled-oscillator circuit

Disclosed is a temperature sensor including a first current generator configured to generate a proportional to absolute temperature (PTAT) current, a second current generator configured to generate an inverse PTAT (IPTAT) current, the PTAT current and IPTAT current being combined to form a reference current having a sensitivity relative to temperature, a plurality of current mirrors to adjust the sensitivity and gain of the reference current, and a variable resistor to set an output calibration voltage based on the generated current.

Temperature sensor and calibration method thereof having high accuracy

A communication unit () is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one of at least one master device and at least one slave device comprises a demodulator circuit () configured to: receive a modulated embedded master-slave clock signal () that comprises a system clock signal () with an embedded frame start signal (); demodulate the modulated embedded master-slave clock signal (); and re-create therefrom the system clock signal () and the frame start signal ().

Communication unit, integrated circuit and method for clock distribution and synchronization

A Time to Digital converter (TDC) may have a Vernier architecture of multiple successive modules arranged in series. Each of the modules may output an indication of a differential in phase between two received signals. Each module may include two signal lines for the received signals, and it may be desirable to calibrate the two signal lines. To this end, a signal output from a proceeding module may be provided to both signal lines of a succeeding module and used as a reference or calibration signal to calibrate the two signal lines of the module.

System and method for calibrating a time to digital converter device

A digital synthesizer includes a ramp generator that generates a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO, that receives the FCW signal and outputs a DCO signal; and a feedback loop that includes a dual time-to-digital converter, TDC, circuit to measure a delay between a representation of the DCO signal and a reference signal. The TDC circuit comprises a medium-resolution TDC circuit coupled to a fine-resolution TDC circuit; and a phase comparator coupled to the ramp generator that compares a phase of the FCW signal output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The medium-resolution TDC circuit comprises a plurality of individual delay cells, where each of the plurality of individual delay cells is coupled to a respective individual fine-resolution TDC circuit.

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Larra, France

Birama Goumballa