Texas Instruments Corporation

Biraja Prasad Dash

Dimitar Trifonov

Ravinthiran Balasingam

Tony Ray Larson

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

Level shifter circuit generating bipolar clock signals

A six phase capacitively coupled chopper amplifier. Two phases provide a zeroing phase to zero the feedback capacitors and set the input common mode value. Two phases provide a passive transfer of an input charge from the input capacitors to the zeroed feedback capacitors. The final two phases are chopping and amplification phases. The zeroing phases address the input common mode without the need for biasing resistors. The passive transfer phases resolve the glitching that occurs if the feedback capacitors have to be recharged on each cycle of the chopping clock. Resolving the glitching and the charge time allows the frequency of the amplifier to increase.

Capacitively coupled chopper amplifier

A circuit, comprising an input chopper configured to receive an input signal, a differential amplifier having an input coupled to an output of the input chopper, a current mode chopping circuit coupled to an output of the differential amplifier, and a first current mirror bias transistor pair coupled between a voltage supply and the current mode chopping circuit.

Current mode chopper amplifier

Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.

Growing community of inventors

Tucson, AZ, United States of America

Biraja Prasad Dash