International Business Machines Corporation

Macronix International Co., Ltd.

Qimonda Ag

Qimonda North America Corporation

Bipin Rajendran

Chung H Lam

Matthew Joseph Breitwisch

Dharmendra S Modha

Hsiang-Lan Lung

Daniel Joseph Friedman

Jose A Tierno

Alejandro Gabriel Schrott

Robert K Montoye

Seongwon Kim

Yong Liu

Thomas Happ

Roger W Cheek

Leland Chang

Eric Andrew Joseph

Yu Zhu

Min Yang

Steven Kyle Esser

Jae-sun Seo

Bernard V Brezzo

Ming-Hsiu Lee

Erh-Kun Lai

Tak H Ning

Martin Michael Frank

Michele M Franceschini

Brian L Ji

Mark B Ritter

Catherine Anne Dubourdieu

Mukta G Farooq

Luis Alfonso Lastras-Montano

Chao-I Wu

Eren Kursun

Yen-Hao Shih

Tze-Chiang Chen

Sarunya Bangsaruntip

Dennis Merton Newns

Matthew Joseph BrightSky

Bruce Gordon Elmegreen

Bryan L Jackson

Mary Beth Rothwell

Simone Raoux

Gary S Ditlow

Luis A Lastras

Gary William Maier

Daniel Krebs

Ralph Linsker

Roger D Traub

Shoaib HasanZaidi

Thomas Nirschi

Chung Hon Lam

One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

Reconfigurable and customizable general-purpose circuits for neural networks

Aspects include a method for generating a signal in response to an event. The method includes receiving, from a clock signal generator, a clock signal, wherein the clock signal has a fixed clock period. The method further includes receiving an indication of a pulse and, responsive to receiving the indication of the pulse, generating an output comprising a high voltage having a starting time and an ending time. The starting time is a first time when the indication of the asynchronous event is received, and the ending time is a second time at one fixed clocked period from the starting time.

Global timing generator

Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

An example embodiment disclosed is a process for fabricating a phase change memory cell. The method includes forming a bottom electrode, creating a pore in an insulating layer above the bottom electrode, depositing piezoelectric material in the pore, depositing phase change material in the pore proximate the piezoelectric material, and forming a top electrode over the phase change material. Depositing the piezoelectric material in the pore may include conforming the piezoelectric material to at least one wall defining the pore such that the piezoelectric material is deposited between the phase change material and the wall. The conformal deposition may be achieved by chemical vapor deposition (CVD) or by atomic layer deposition (ALD).

Phase change material cell with piezoelectric or ferroelectric stress inducer liner

An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.

Integrated circuit including vertical diode

A three dimensional (3D) stack of phase change memory (PCM) devices which includes PCM devices stacked in a 3D array, the PCM devices having memory regions; a memory management unit on at least one of the PCM devices; a stack controller in the memory management unit to monitor an ambient device temperature (T) with respect to a neighborhood of memory regions in the PCM devices and to adjust a programming current with respect to at least one of the memory regions in the neighborhood of memory regions in accordance with the T. Also disclosed is a method of programming a PCM device.

Phase change memory management

Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.

Polysilicon pillar bipolar transistor with self-aligned memory element

Growing community of inventors

White Plains, NY, United States of America

Bipin Rajendran