Ncr Corporation

Bipin D Parikh

Prabodh M Dharia

John J Kurtz

Haresh C Patnaik

Bhagubhai K Patel

John K Burkey

Herbert D McClain

Alfred D Jenkins

Prakash Y Mahajan

A digital communication system employs a technique of effectively controlling the size of the bytes making up a field of data to be serially transmitted from one station to another, particularly one wherein the byte size may be selectively changed during the transmission of the data field. Assembly of a transmitted data field is controlled so that it includes an encoded data byte, termed a first pre-header byte, which contains information as to whether or not a change in the byte size of the data field is to occur. If the first pre-header byte indicates the occurrence of a byte size change, it also will contain a code representative of the size of the change. In addition, for a change in byte size, a second encoded data byte, termed a second pre-header or count byte is generated and immediately follows the first pre-header byte. The count byte contains information which specifies the length of that portion of the data field which precedes the occurrence of the change in byte size. Thereafter, following these pre-header bytes are a number of bytes of a first byte length (usually eight bits), which number is designated by the count byte, succeeded by those data bytes whose size is that specified in the first pre-header byte.

Digital communications system utilizing controllable field size

Communications between processor terminals are carried out through the use of communication adapters. Each adapter receives selected control signals for transmitting or receiving data over a serial communication link to or from a remote terminal. The transmission portion of an adapter includes pretransmission control circuitry which receives control signals and stores transmission control signals which are used to control the format and serial transmission of a frame of data to a remote terminal. Each frame of data is begun and terminated with a uniquely encoded flag byte. Following the first flag byte are successive address and control fields. An optional information field may follow the control field and may include encoded information designating a dynamic change in the byte size of the data. Immediately following the information field, a frame check sequence field, generated in accordance with the contents of each of the address, control, and information field, is transmitted, followed by a frame terminating flag byte. In order to enable the adapter to receive a serial data stream from a remote terminal and couple this received data to its assoicated processor, the adpater includes pre-reception control and direct memory access control circuitry coupled over the common control bus to the common control module and its associated memory. Upon completely disassembling a frame, the adapter generates appropriate status signals and an interrupt is supplied to the common control.

Digital data communication adapter

A technique and implementation of generating and supplying synchronization and error checking signals to a serially transmitted data stream includes the generation of flag bytes which define the end boundaries of the serial data stream, an abort character for aborting the transmission of a frame of data in response to certain conditions, and a diagnostic evaluation character inserted into the data stream. In addition, the invention provides a technique for ensuring that the unique binary code by which a flag byte is defined occurs in the transmitted data stream only where intended. The flag code has been chosen to contain a prescribed number of consecutive one bits, (i.e. -- six) flanked by zeroes, and circuitry monitors the contents of a data frame as it is being serialized out for transmission to a remote terminal at times other than during flag transmission. When five consecutive one bits are detected, serializing out of the next bit in the data is interrupted, and a dummy zero bit is inserted prior to the next bit. As a result, the transmitted frame of data will contain no more than five consecutive one bits, except during the flag bytes, (or an abort character) thus ensuring proper synchronization of the end points of the frame. At the receiver terminal, detection and decoding circuitry also monitors the number of consecutive one's in the received data stream. When five consecutive one's are detected, the receiver decoder circuitry checks to see whether the next bit is a dummy zero bit. If the next bit is a zero bit, it is deleted so that the intended data will be correctly reassembled.

System for controlling synchronization in a digital communication system

A digital timing recovery circuit is disclosed for synchronously transmitting digitally encoded data in a multiterminal configuration between a data processor and a plurality of data terminals associated therewith. Phase shifted synchronous data from the data processor is continuously compared with a newly generated synchronous clock generated at a repeater interposed along the communication line for minimization of the time differential between the retiming clock and the transmitted data. The data transitions enable a digitally implemented one-shot, which generates pulses, the leading edges of which pulses enable a difference counter, while the leading edges of the retiming clock pulses disable the counter. The difference counter output is sampled in a digital phase locked loop to derive the number of cycles of a stable oscillator which occur between the two aforementioned leading edges of the generated pulses. A difference of less than a predetermined count such as two, results in no correction of the retiming clock, a difference count greater than such predetermined amount, such as a count of three through seven, advances the clock by adding a pulse to the retiming clock, and a difference of more than a predetermined number of counts, such as eight, retards the clock by subtracting a pulse from the retiming clock. Thus, continuous digital adjustment of the synchronous clock is provided to maintain the counter difference below a predetermined count, such as two, which serves to resynchronize bit-shifted data with the retiming clock for retransmission into the communications channel.

Data communications system with improved digital phase-locked loop

A data communication system for asynchronously transmitting intermittently generated digitally encoded data between a data processor and a plurality of data terminals associated therewith is disclosed wherein the allowable communications line distance between the data processor and the terminals is substantially increased. Asynchronous data from the terminals is intercepted by a novel repeater, retimed in accordance with a newly generated retiming clock to eliminate bit-shift or other errors from the data, and retransmitted to the central processor over an extended length transmission line, with the repeater being substantially transparent to the flow of data. Decoding of an appropriate code by the repeater which is indicative of the receipt of a data character causes the switching from a data derived clock to a retiming clock for reencoding and retransmission of the data.

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Cambridge, OH, United States of America

Bipin D Parikh