Marvellworld Trade Ltd.

Marvell International Limited

Texas Instruments Corporation

Synaptics Corporation

Bipasha Ghosh

Nikhil Balram

Sanjay Saran Garg

Richard David Taylor

Vipin Namboodiri

Shilpi Sahu

Gwyn Edwards

Loren Tomasi

Kaip Sridhar

Sujith Srinivasan

Raghu Nandan Srinivasa

Snehamay Sinha

Stephen N Kiel

Edwards Gwyn

The invention includes a system and the associated method for decoding multiple video signals. The video signals may be component video, composite video or s-video signals each having multiple portions using a multimode video decoder. A selection stage may combine the multiple video signals and select some of their video signal portions for processing. The selection stage may time-multiplex some of the video signal portions. An analog to digital conversion stage may be shared by the time-multiplexing of the video signals. A decoder stage may decode the various signal portions and provide decoded output video signals. These feature may reduce the overall cost of the system. Various clock signals may be used to operate various stages of a multimode video decoder. Some of the clock signals may run at different frequencies and others may operate at a different phase.

Shared memory multi video channel display apparatus and methods

A shared memory video processor including signal processing circuitry. The signal processing circuitry may enable a noise reducer and a de-interlacer to share access to field buffers in a memory device to store various field lines. Some of the stored field lines may also be shared within the signal processing circuitry. The sharing of some stored field lines reduces overall memory bandwidth and capacity requirements. The signal processing circuitry may be capable of performing multiple field line processing. A set of field line buffers may be provided to store field lines for multiple field segments and may provide the data to the corresponding inputs of the signal processing circuitry. To further reduce storage, some of the field line buffers may also be shared among the signal processing circuitry.

A scaler positioning module may receive a video signal selected from among a plurality of video signals. The scaler positioning module may include scaler slots for arranging the signal path of the selected video signal through at least one scaler in the scaler positioning module. The scaler slots may enable the scaler positioning module to operate in three modes. The three modes may enable the scaler positioning module to output scaled data without memory operations, scale prior to a memory write, and scale after a memory read. A blank time optimizer (BTO) may receive data from the scaler positioning module at a first clock rate and distributed memory accesses based on a bandwidth requirement determination. The BTO may access memory at a second clock rate. The second clock rate may be slower than the first which may reduce memory bandwidth and enable another video signal to access memory faster.

A color management unit is architected to achieve higher-quality appearance used in various video formats and to enable improvements in picture contrast and colorfulness. The color management unit comprises an optional input color space converter to convert the input digital video to a desired color space, an adaptive contrast enhancer to apply contrast improvement algorithms in response to different scenes in either manual or automatic modes, intelligent color remapping for enhancing selected colors, sRGB compliance to produce a video display that is uniform over different monitors, global color and brightness controls to combine global processing and color conversion, gamut compression to maintain pixel validity in color space conversion, and gamma correction to compensate for nonlinear characteristics of an output display.

Color management unit

A method for estimating noise in an integrated circuit substrate. A model file is created for a technology process for fabricating the integrated circuit. Noise generated by a digital circuit and input/output circuitry to be implemented in the integrated circuit are estimated. A substrate netlist is generated for the integrated circuit. A floorplan is determined for the integrated circuit. Transient simulations are run with predetermined input values. Finally, it is determined if predetermined noise requirements are met in results of the transient simulations.

Method for estimating substrate noise in mixed signal integrated circuits

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Bengaluru, India

Bipasha Ghosh