Samsung Electronics Co., Ltd.

Bio Kim

Yujin Kim

Jaeyoung Ahn

Jung Ho Kim

Hyung Joon Kim

Junggeun Jee

Kihyun Hwang

Jae Young Ahn

SeungHyun Lim

Dongwoo Kim

Young Jin Noh

Kyong-Won An

Jumi Yun

Jaehyun Yang

Sookyeom Yong

Young Seon Son

Youngjun Cheon

Kwangmin Park

Hanmei Choi

Dongchul Yoo

Young-jin Noh

Woojin Jang

Woo Jin Jang

Youngseon Son

Jun Kyu Yang

Eunyeoung Choi

Kyong Won An

Philouk Nam

Kyongwon An

Ju Mi Yun

Su Jin Shin

Jae Ho Choi

Ji-Hoon Choi

Seung Hyun Lim

Toshiro Nakanishi

Yong Seok Cho

Jintae Noh

Gukhyon Yon

Jeon Il Lee

Eun Yeoung Choi

Hanvit Yang

Su-Jin Shin

Sung Hae Lee

Kwang Min Park

Dong Chul Yoo

Joong Yun Ra

JaeHo Choi

Young Wan Kim

Byong Hyun Jang

A semiconductor device includes a peripheral circuit structure including: a first substrate, circuit devices on the first substrate, a lower wiring structure electrically connected to the circuit devices, a lower insulating layer covering the lower wiring structure, and a diffusion barrier layer on the lower insulating layer; and a memory cell structure including a second substrate including first and second regions on the peripheral circuit structure, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate in the first region and extending in a second direction perpendicular to the first direction to form a staircase shape in the second region, and channel structures penetrating the gate electrodes in the first direction and each including a channel layer. The diffusion barrier layer includes a first material layer having a hydrogen permeability lower than a hydrogen permeability of silicon nitride.

Semiconductor devices and data storage systems including the same

A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.

Three-dimensional semiconductor memory devices

A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.

Vertical memory devices and methods of manufacturing the same

A semiconductor device includes a lower stack structure on a substrate, an upper stack structure on the lower stack structure, and a channel structure in a channel hole formed through the upper stack structure and the lower stack structure. The channel hole includes a lower channel hole in the lower stack structure, an upper channel hole in the upper stack structure, and a partial extension portion adjacent to an interface between the lower stack structure and the upper stack structure. The partial extension portion is in fluid communication with the lower channel hole and the upper channel hole. A lateral width of the partial extension portion may be greater than a lateral width of the upper channel hole adjacent to the partial extension portion and greater than a lateral width of the upper channel hole adjacent to the partial extension portion.

Semiconductor device including partially enlarged channel hole

An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

Integrated circuit memory devices having impurity-doped dielectric regions therein and methods of forming same

A semiconductor device including a dielectric layer is provided. The semiconductor device includes a stack structure, and a vertical structure within the stack structure. The vertical structure includes a lower region having a first width and an upper region having a second width, greater than the first width. The vertical structure further includes two dielectric layers of which respective ratios of lower thicknesses in the lower region to upper thicknesses in the upper region are different from each other.

Semiconductor device including a dielectric layer

A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.

Semiconductor device

A method of manufacturing a semiconductor device includes forming a mold structure including alternately stacked mold insulating and sacrificial layers on a substrate, forming a vertical structure through the mold structure, forming side openings by removing the sacrificial, forming a preliminary dielectric layer in the side openings, forming a dielectric layer by heat-treating the preliminary dielectric layer, removing a surface layer of the dielectric layer, forming a first conductive layer covering the dielectric layer in the side openings, and forming a second conductive layer covering the first conductive layer and filling the side openings.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes forming insulation layers and sacrificial layers that are alternately and repeatedly stacked on top of each other a substrate, forming a vertical hole that penetrates the insulation layers and the sacrificial layers, and forming a vertical channel structure in the vertical hole. The forming the vertical channel structure includes forming a blocking insulation layer, a charge storage layer, a tunnel insulation layer, and a semiconductor pattern. The forming the blocking insulation layer includes forming a first oxidation target layer, oxidizing the first oxidation target layer to form a first sub-blocking layer, and forming a second sub-blocking layer. The first sub-blocking layer is formed between the second sub-blocking layer and an inner sidewall of the vertical hole.

Methods of manufacturing semiconductor device having a blocking insulation layer

Growing community of inventors

Seoul, South Korea

Bio Kim