Globalfoundries Inc.

Binu Jose

Venkatraghavan Bringivijayaraghavan

Sreejith Chidambaran

Sreenivasula Reddy Dhani Reddy

George Maria Braceras

Krishnan Santhana Rengarajan

A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.

Write assist

Memory cells with read assist schemes and methods of use are provided. The memory includes a plurality of rows and columns, each of which include a memory cell having a pull-down device. The memory further includes at least one boost circuit connected to each of the memory cells and which provides a negative boost signal to the pull-down devices during read access.

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Pune, India

Binu Jose