International Business Machines Corporation

Binta Minesh Patel

George McNeil Lattimore

Todd Alan Christensen

Gregory John Uhlmann

Anthony Gus Aipperspach

Christopher McCall Durham

Gus Wai-Yan Yeung

Jose Angel Paredes

Donald George Mikan, Jr

Bruce Joseph Ronchetti

Salvatore Nicholas Storino

Nghia Van Phan

Michael James Rohn

Peter Gursen Klim

Bryan Joe Talik

Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arrays

A silicon-on-insulator digital circuit combination having a body voltage control stage and a voltage clamp stage. The body voltage control stage is responsive to an input control signal to provide an output driver signal. The body voltage control stage has a first transistor with a terminal for electrically-coupling to a combinational logic circuit, and a body contact electrically-coupled to the input control signal such that a threshold voltage of the transistor is reduced when the transistor is placed in an active state. It can be readily appreciated that the reduced threshold voltage of the transistor increases the transition rate for the first transistor to an inactive state in response to the input control signal. The voltage clamp stage has a second transistor responsive to the input control signal such that the terminal is electrically-coupled to a reference voltage when the first transistor is in the inactive state.

Circuit driver on SOI for merged logic and memory circuits

A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, a discharge transistor, multiple input transistors, and a supplemental precharge transistor. Connected to a power supply, the precharge transistor receives a clock input. The discharge transistor is connected to ground and also receives the clock input. The input transistors, which are coupled between the precharge transistor and the discharge transistor, each receives a signal input. The supplemental precharge transistor is connected to the power supply and to a body of each of the input transistors. The supplemental precharge transistor also receives the same clock input as the precharge transistor.

Silicon on insulator domino logic circuits

A multi-threaded memory (and associated method) for use in a multi-threaded computer system in which plural threads are used with a single processor. The multi-threaded memory includes: multi-threaded storage cells; at least one write decoder supplying information to a selected multi-threaded storage cell; and at least one read decoder accessing information from a selected multi-threaded storage cell. Each of the multi-threaded storage cells includes: N storage elements, where N.gtoreq.2, each of the N storage elements having a thread-correspondent content; a write interface supplying information to the intra-cell storage elements; and a read interface reading information from the intra-cell storage elements. At least one of the intra-cell read and write interfaces selects one of the thread-correspondent contents based at least in part by identifying the corresponding thread to achieve intra-cell thread-correspondent content selection.

Multi-threaded cell for a memory

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Round Rock, TX, United States of America

Binta Minesh Patel