Intel Corporation

Apple Inc.

Binta M Patel

Ashoke Ravi

William Li

Cho-Ying Lu

Khoa Nguyen

Maneesha Yellepeddi

Lance E Hacking

Blaise B Fanning

Rajesh Bhikhubhai Patel

Belliappa Manavattira Kuttanna

Ashish V Choubal

Sankaran M Menon

Manoj Sinha

Nancy G Woodbridge

Terry M Fletcher

Bo Jiang

Steven Scott Varnum

Gian Gerosa

Michael E Altenburg

David K Dean

Amrish Kontu

A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.

Systems and methods for frequency domain calibration and characterization

Observability of internal system-on-chip signals is a difficult problem and it is particularly difficult to observe and debug transactions with different clock domains. However, one embodiment provides observability of internal signals from multiple internal blocks having varying clock domains such as synchronous (common clock) and asynchronous (non common clock) domains. An embodiment provides simultaneous observability of debug data from both synchronous and asynchronous clock domains. An embodiment may also allow sending debug data from both synchronous and asynchronous domains from the SoC. One embodiment outputs internal signals on output pins of the SoC, thereby allowing transactions from one clock domain to be tracked to another clock domain and allowing for the determination of the relationship between the data of differing clock domains. Other embodiments are described herein.

Observing embedded signals of varying clock domains by fowarding signals within a system on a chip concurrently with a logic module clock signal

A method to reduce idle leakage power in I/O pins of an integrated circuit using external circuitry. Initially, I/O pins on a package are subdivided into those that will also remain powered up and those that will power down during idle state. When a system enters a low power mode, a signal is sent to the external circuitry. The signal notifies the I/O pins that always remain powered up to notify the external circuitry to power down the other set of I/O pins.

Reducing idle leakage power in an IC

Techniques involving the transfer of signals across interconnection media are disclosed. For instance, an apparatus may include an apparatus having an interconnection medium, a first device that may drive the interconnection medium, and a second device. The second device may include a pull-up resistor that is selectively coupled between the interconnection medium and a power source. For instance, the second device may disconnect a power source from the interconnection medium when the first device is in a power saving operational state. Otherwise, the pull-up resistance is coupled between the power source and the interconnection medium.

Termination techniques for bus interfaces

A front side bus swizzle mechanism modifies the front side (address and data) bus on a chip so that, when the chip is positioned on one side of a printed circuit board, connection to a second chip located on the opposite side of the printed circuit board is simplified. The simplified connection may result in less complexity and minimize the consumption of additional printed circuit board real estate.

Bus interconnect switching mechanism

A system may include detection of a low signal received from a transmission line, and uncoupling of a termination circuit from the transmission line in response to the detected low signal. In some aspects, a transition of a strobe signal is then detected, and the termination circuit is coupled to the transmission line in response to the detected transition.

Dynamic transmission line termination

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Austin, TX, United States of America

Binta M Patel